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Data Sheet

AD6679

Rev. B | Page 15 of 81

D15

CLK+

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

90° PHASE ADJUST1

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

270° PHASE ADJUST2

SYNC+

FCO–

(FRAME CLOCK OUTPUT)3

FCO+

STATUS+

(OVERRANGE STATUS BIT)

STATUS–

APERTURE DELAY

N + x

N – 1

N + y

N + z

N + 33

N + 34

N + 35

DATA0±

DATA7±

I0[N]

EVEN

N + 36

N + 37

N + 38

N + 39

VIN±x

190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

3FRAME CLOCK OUTPUT SUPPORTS THREE MODES OF OPERATION:

1) ENABLED (ALWAYS ON)

2) DISABLED (ALWAYS OFF)

3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDORANDOM BIT)

4STATUS BIT SELECTED BY THE OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP.

PAR4

D15

PAR

D14

OVR

D15

PAR

D14

OVR

D15

PAR

D14

OVR

D15

PAR

D14

OVR

D15

PAR

CLK–

FRAME 0

FRAME 1

SYNC–

tCLK

tCH

tDCO

tFCO

tPD

tFRAME

I0[N]

ODD

Q0[N]

EVEN

Q0[N]

ODD

I0[N + 1]

EVEN

I0[N + 1]

ODD

Q0[N + 1]

EVEN

Q0[N + 1]

ODD

SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO/FCO DIVIDERS TO BE RESET

FIXED DELAY FROM SYNC EVENT

TO DCO KNOWN PHASE

tSKEWF

tSKEWR

2 × tCLK

Figure 9. LVDS Byte Mode—Two Virtual Converters, One DDC (I/Q Decimate by 4)

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