AD6676EBZ datasheet(54/90 Pages) AD

54 / 90 page

AD6676

Data Sheet

Rev. D | Page 54 of 90

–5

–10

–15

–20

–25

–30

–35

100

200

300

400

500

600

800

1000

700

900

FREQUENCY (MHz)

WITHOUT

TDK LPF

WITH TDK LPF

Figure 129. TDK Filter Has Minimal Effect on the Pass Band IF Response

Table 22. Typical Alias Rejection for Different IF and ADC

Combinations with TDK 500 MHz Low-Pass Filter Added

FADC (MHz)

IF (MHz)

FADC − IF Alias

Rejection (dBc)

FADC + IF Alias

Rejection (dBc)

2000

150

2400

200

2800

300

3200

400

A 1:1 balun is required in applications where the last amplification

stage is single-ended with a ZOUT of 50 Ω. This is typically the

case in a VHF receiver application where a gain block, such as

the ADL5541 to ADL5545 series, precedes the AD6676 for

preamplification.

VIN+

VIN–

1nF

ADL5541

ADL5545

DEVICES

VHF

SIGNAL

1:1 BALUN

(MABA-007159)

AD6676

Figure 130. RF Line-Up for Direct Sampling VHF Application

For many RF receiver applications, this differential signal may

originate from a RF-to-IF mixer whose output impedance often

falls within a 50 Ω to 200 Ω range. A low order matching network

that also serves as a low-pass roofing filter can compensate for

the mismatch impedance. It is worth noting that the impedance

mismatch between a source/load mismatch of 200 Ω/60 Ω and

100 Ω/60 Ω is approximately 1.5 dB and 0.3 dB, respectively. This

low mismatch loss may be tolerable for some applications

seeking a wide, low ripple IF pass band, especially considering

the loss of a higher order matching network with finite Q

components. Lastly, it is possible to reduce the ADC maximum

input power requirements slightly to compensate for this low

loss with minimal loss in dynamic range.

Other receiver applications in the VHF band may prefer that

the AD6676 directly digitize the signal. Typically, the radio lineup

may include a low NF gain block whose single-ended output is

converted to a differential output via an ac-coupled balun. The

amplitude/phase balance requirements of balun can be relaxed

(compared to traditional pipeline ADCs) because the even order

harmonics that are sensitive to balance fall outside the pass band.

Note that the second harmonic of the gain block still must fall

outside the VHF pass band so that it can also be digitally filtered.

Some additional considerations pertaining to the analog input

are as follows:



AC coupling with 10 nF or greater capacitors to the VIN±

input is required to a maintain 1 V common-mode voltage.

Note that this capacitor provides a high-pass response with

the AD6676 input impedance and thus must be sized

accordingly for low IF applications to prevent excessive

droop on the lower pass band response.



A series 10 Ω resistor and 0.1 μF decoupling capacitor is

recommended between the 2.5 V supply and first resonators

to provide additional filtering of supply induced noise and

ADC common-mode currents.



The feedback DAC (operating up to 3.2 GHz) also

generates high frequency content (that is, images, clock

feedthrough and shaped noise) that is ideally absorbed by

the internal source follower. Due to its finite impedance at

the higher frequencies, a small amount of this undesired

signal content leaks through the attenuator path back to

the VIN± input. Passive mixers are particularly susceptible

to this signal content due to poor isolation between the IF

and RF ports while passive mixers with on-chip IF amps

and active mixers provide a greater degree of reverse

isolation. A simple third-order roofing filter typically

provides sufficient rejection to suppress these ADC

artifacts while also suppressing the larger M × N artifacts

of the mixer. Note that this filter must be designed as two

single-ended, pi network filters with shunt capacitors

located next to the VIN± pins to steer this undesired signal

content to ground. Also, use care in component selection

and layout to reduce parasitics that can cause unanticipated

peaking in the stop-band region of the filter response.

CLOCK INPUT CONSIDERATIONS

The AD6676 Σ-Δ ADC operates with an internal ADC clock

rate (FADC) between 2.0 GSPS to 3.2 GSPS. The clock signal can

originate from an external clock source or, alternatively, from its

on-chip clock synthesizer. Consider an external clock source if

the on-chip synthesizer phase noise or spurious level is not

deemed sufficient or if the desired FADC falls below the 2.94 GHz

to 3.2 GHz range of the VCO. Referring to Figure 60, the self-

biased clock receiver is configured as either a differential or single-

ended receiver, depending on whether the clock synthesizer is

disabled. In either case, the external clock source must be ac

coupled to the AD6676 CLK± input and meet the minimum

specified input level and slew rate. Also, clock jitter and phase

noise must always be a concern in selecting the clock source.

When the clock synthesizer is enabled, the CLK± inputs are

connected to CMOS inverters as shown in Figure 60. These

inverters are self-biased at approximately 0.55 V and present an

input resistance exceeding 1.2 kΩ when Bit 2 of Register 0x2BB

is set.

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