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drives an external MOSFET (Q3) to supply the GTL bus

Initialization

The HIP6017 automatically initializes upon receipt of input

power. By the time the soft-start (SS) voltage reaches 4V,

the 3.3V input has to be high enough such that the two linear

threshold. A typical ATX supply meets this requirement. The

Power-On Reset (POR) function continually monitors the

input supply voltages. The POR monitors the bias voltage

the OCSET1 pin. The normal level on OCSET1 is equal to

protection). The POR function initiates soft-start operation

after both input supply voltages exceed their POR

thresholds.

Soft-Start

The POR function initiates the soft-start sequence. Initially,

the voltage on the SS pin rapidly increases to approximately

1V (this minimizes the soft-start interval). Then an internal

11

the SS pin to 4V. The PWM error amplifier reference input

(+ terminal) and output (COMP1 pin) are clamped to a level

proportional to the SS pin voltage. As the SS pin voltage

ramps from 1V to 4V, the output clamp allows generation of

PHASE pulses of increasing width that charge the output

capacitor(s). After this initial stage, the reference input clamp

slows the output voltage rate-of-rise and provides a smooth

transition to the final set voltage. Additionally, both linear

regulator’s reference inputs are clamped to a voltage

proportional to the SS pin voltage. This method provides a

rapid and controlled output voltage rise.

Figure 6 shows the soft-start sequence for the typical

application. At T0 the SS voltage rapidly increases to

approximately 1V. At T1, the SS pin and error amplifier

output voltage reach the valley of the oscillator’s triangle

wave. The oscillator’s triangular waveform is compared to

the clamped error amplifier output voltage. As the SS pin

voltage increases, the pulse-width on the PHASE pin

increases. The interval of increasing pulse-width continues

until each output reaches sufficient voltage to transfer

control to the input reference clamp. If we consider the 2.0V

the interval between T2 and T3, the error amplifier reference

ramps to the final value and the converter regulates the

output to a voltage proportional to the SS pin voltage. At T3

the input clamp voltage exceeds the reference voltage and

the output voltage is in regulation.

The remaining outputs are also programmed to follow the

initially follows a ramp similar to that of the PWM output.

When each output reaches sufficient voltage the input

reference clamp slows the rate of output voltage rise. The

PGOOD signal toggles ‘high’ when all output voltage levels

have exceeded their under-voltage levels. See the Soft-Start

Interval section under Applications Guidelines for a

procedure to determine the soft-start interval.

Fault Protection

All three outputs are monitored and protected against

extreme overload. A sustained overload on any linear

regulator output or an over-voltage on the PWM output

disables all converters and drives the FAULT/RT pin to VCC.

Figure 7 shows a simplified schematic of the fault logic. An

over-voltage detected on VSEN1 immediately sets the fault

latch. A sequence of three over-current fault signals also

FIGURE 6. SOFT-START INTERVAL

0V

0V

0V

TIME

PGOOD

SOFT-START

(1V/DIV)

OUTPUT

(0.5V/DIV)

VOLTAGES

T1

T2

T3

T0

(2V/DIV)

T4

FAULT

LATCH

S

R

Q

POR

COUNTER

OC1

OV

LUV

+

-

+

-

0.15V

4V

SS

VCC

FAULT

R

FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC

UP

OVER

CURRENT

LATCH

INHIBIT

S

R

Q

S

HIP6017