TPS2236DAPG4 datasheet(4/26 Pages) TI

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TPS2231

TPS2236

SLVS536B – JULY 2004 – REVISED JANUARY 2005

ELECTRICAL CHARACTERISTICS (continued)

J = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,

I(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

II(AUXIN)

200

320

Normal operation

II(3.3VIN)

17.5

µA

of TPS2236

Outputs are unloaded, TJ[–40,

II(1.5VIN)

5.5

120

°C] (include CPPEx and CPUSBx

II(AUXIN)

120

210

logic pullup currents)

Normal operation

II(3.3VIN)

µA

of TPS2231

II(1.5VIN)

2.5

Total input

quiescent current

II(AUXIN)

250

440

Shutdown mode of

II(3.3VIN)

3.5

µA

CPUSB = CPPE = 0 V SHDN = 0 V

TPS2236

(discharge FETs are on) (include

II(1.5VIN)

0.1

CPPEx and CPUSBx logic pullup

II(AUXIN)

144

270

currents and SHDN pullup current) TJ

Shutdown mode of

[–40, 120

°C]

II(3.3VIN)

3.5

µA

TPS2231

II(1.5VIN)

0.5

II(AUXIN)

100

SHDN = 3.3 V,

TPS2236

II(3.3VIN)

0.1

100

µA

CPUSB = CPPE = 3.3 V (no card

II(1.5VIN)

0.1

100

Forward leakage

present, discharge FETs are on);

Ilkg(FWD)

current

current measured at input pins

II(AUXIN)

TJ = 120°C, includes RCLKEN

TPS2231

II(3.3VIN)

0.1

µA

pullup current

II(1.5VIN)

0.1

TJ = 25°C

0.1

II(AUXOUT)

µA

TJ = 120°C

VO(AUXOUT) = VO(3.3VOUT)= 3.3 V;

Reverse leakage

TJ = 25°C

0.1

VO(1.5VOUT) = 1.5 V; All voltage inputs

Ilkg(RVS)

current (TPS2236 II(3.3VOUT)

µA

are grounded (current measured

TJ = 120°C

and TPS2231)

from output pins going in)

TJ = 25°C

0.1

II(1.5VOUT)

µA

TJ = 120°C

LOGIC SECTION (SYSRST, SHDNx, STBYx, PERSTx, RCLKENx, OCx, CPUSBx, CPPEx)

SYSRST = 3.6 V, sinking

I(/SYSRST)

Input

µA

SYSRST = 0 V, sourcing

SHDNx = 3.6 V, sinking

I(/SHDNx)

Input

µA

SHDNx = 0 V, sourcing

Logic input

STBYx = 3.6 V, sinking

supply current

I(/STBYx)

Input

µA

STBYx = 0 V, sourcing

I(RCLKENx)

Input

RCLKENx = 0 V, sourcing

µA

CPUSB or CPPE = 0 V, sinking

I(/CPUSBx) or

Inputs

µA

I(/CPPEx)

CPUSB or CPPE = 3.6 V, sourcing

High level

Logic input

voltage

Low level

0.8

RCLEN output low voltage

Output

IO(RCLKEN) = 60 µA

0.4

3.3VOUT falling

2.7

PERST assertion threshold of output voltage (PERST

asserted when any output voltage falls below the

AUXOUT falling

2.7

threshold)

1.5VOUT falling

1.2

1.35

3.3VOUT, AUXOUT, or 1.5VOUT

PERST assertion delay from output voltage

500

falling

3.3VOUT, AUXOUT, and 1.5VOUT

PERST de-assertion delay from output voltage

rising within tolerance

Max time from SYSRST asserted or

PERST assertion delay from SYSRST

500

de-asserted

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