CS62180B datasheet(33/50 Pages) CIRRUS

33 / 50 page

HARDWARE MODE

For stand alone applications or prototyping in

which the device is to operate without a host

processor, the CS62180B can be

configured to run in hardware mode by tying the

Serial Port Select pin (SPS) to ground (VSS).

This disables the serial port and redefines pins

14-18 (16-20, PLCC) as mode control pins. All

registers are cleared, with the exception of the

control bits which are mapped to the mode con-

trol pins, and TCR.4, which is set to "1",

enabling robbed bit signaling. This means that,

with the exception of robbed bit signaling, the

configuration of the CS62180B

in hardware mode is the same as if it were in

host mode with all control bits cleared. Dynamic

control of a few of the control bits is provided

by mapping them directly to pins 14-18 (16-20,

PLCC). Operation of these pins is described in

Hardware Mode Control Pins and Table 2. Note

that the SLC-96

® and T1DM framing formats

are not supported in the hardware mode.

When operating in hardware mode, bit-robbed

signaling is enabled for all channels. Signaling

data sampled from TABCD is inserted into the

8th bit position (LSB) of every DS0 channel dur-

ing signaling frames (every 6th frame). There is

no facility for programming individual channels

clear, however; all channels may be made trans-

parent by tying TABCD to TSER.

When pulling 193SI high for external S-bit in-

sertion in 193S mode, data is sampled from

TLINK and inserted into the F-bits of even

frames. The 193SI pin has no effect when the

device is in 193E mode. When using 193E for-

mat, TLINK is sampled for insertion into every

odd F-bit (FDL). CRC data is internally gener-

ated and cannot be externally supplied.

The receiver will initiate a resync if 2 of the pre-

vious 4 framing bits were in error. It will declare

synchronization after 10 consecutive F-bits are

qualified. When in 193E mode, CRC errors will

be reported on RFER, but not used to qualify

synchronization. Receiver status can be moni-

tored via the status outputs: RYEL, RCL, RBV,

RFER, and RLOS. There is no support for gen-

erating blue alarms or idle code insertion when

in hardware mode.

Hardware Mode Control Pins

Framing Format

The FM pin allows selection of the framing

mode for both transmit and receive sides. Hold-

ing this pin low selects 193S framing mode.

193E framing may be selected by pulling the

FM pin high.

PIN NUMBER

MAPPING

DESCRIPTION

FUNCTION

DIP

PLCC

TCR.2

193S: S-bit Insertion

0 = Internal

1 = External

CCR.4

Framing Mode Select

0 = 193S

1 = 193E

TCR.0

Transmit Yellow Alarm

0 = Disabled

1 = Enabled

CCR.1

B7 Zero Suppression

0 = Transparent

1 = B7 Stuffing

CCR.2

B8ZS Zero Suppression

0 = Disabled

1 = Enabled

Table 2. Hardware Mode Control Pins

CS62180B

DS225PP2

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