CS62180 datasheet(22/50 Pages) CIRRUS

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RECEIVER

The receive sides of the CS62180B

have only three inputs: the clock (RCLK), the in-

coming signal (RPOS/RNEG), and a reset pin

(RST). The receiver determines the framing syn-

chronization of the incoming data, and outputs the

timing information on the six timing clocks:

RLCLK, RCHCLK, RFSYNC, RMSYNC,

RSIGFR, and RSIGSEL. Alarms and error condi-

tions are recorded in the Receive Status Register,

and output in real time on the five status pins:

RYEL, RCL, RBV, RFER, and RLOS. The de-

coded data is separated into it’s component

channel, link, and signaling components and output

on RSER, RLINK, and RABCD respectively.

When in host mode, the Receive Control Register

allows control of the sync algorithm, and insertion

of idle or digital milliwatt (

µ-LAW) codes into in-

dividual DS0 channels. The internal error counters

can be accessed, and the Interrupt Mask Register

can be programmed to specify the conditions under

which a hardware interrupt is generated on INT.

When running in hardware mode, receiver status

can still be monitored on the status pins; and access

to the error counters, sync algorithm, interrupt

mask, and the insertion of idle codes are disabled.

Input Data

The receiver accepts the incoming T1 stream via

RPOS/RNEG in dual-unipolar format. Tying

RPOS/RNEG together disables the bipolar viola-

tion alarm and allows reception of data in NRZ

format. Input data is sampled on the falling edge of

RCLK. Delay from input at RPOS/RNEG to out-

put on RSER is 13 RCLK periods.

Output Data

The receiver will attempt to sync and decode the

framing format selected via CCR.4 and CCR.7.

The decoded T1 stream is output in NRZ format on

RSER, and updated every RCLK period. Output

data is latched on the rising edge of RCLK, and

held until the next update.

Link and signaling data is always output on

RLINK and RABCD respectively, independent of

the transmitter configuration. RABCD outputs the

LSB of every DS0 channel word, whether it is cur-

rently a signaling frame or not. The data is updated

on the channel boundary, concurrent with the MSB,

and held until the next update (8 or 9 bits). RLINK

outputs either S-bit, SLC-96

® DL or FDL bits,

depending on the framing format. Data is up-

dated 1 bit period prior to the FS or FDL frame

and held until the next update (2 frames).

Output Clocks

Several timing clocks are provided for identify-

ing this data. The timing clocks are RLCLK,

RCHCLK, RFSYNC, RMSYNC, RSIGFR, and

RSIGSEL. Logical combination of these six sig-

nals allows easy extraction of any part of the

received data stream. RMSYNC runs on a 50%

duty cycle, and transitions high at the start of

each new superframe output on RSER. RFSYNC

transitions high at the start of every new frame.

Individual DS0 channels are identified by

RCHCLK, which runs on a 50% duty cycle and

transitions high at the MSB of every individual

time slot. Bit level timing is shown in Figure 14.

193S Timing

Link data can be identified by RLCLK, which

goes high for all odd numbered frames. RSIGFR

is high for signaling frames, and low at all other

times. RSIGSEL runs at twice the frequency of

RMSYNC. Logical combination of RMSYNC

and RSIGSEL provides a way to distinguish the

th and 12th frames for external multiplexing of

signaling channels. RMSYNC is high for those

frames containing A signaling bits, and low for

frames containing B bits. Refer to Figure 15 for

a timing diagram.

CS62180B

DS225PP2

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