AD73322LAST datasheet(21/49 Pages) AD

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AD73322L

Rev. A | Page 20 of 48

DAC ADVANCE REGISTER

The loading of the DAC is internally synchronized with the

unloading of the ADC data in each sampling interval. The

default DAC load event happens one SCLK cycle before the

SDOFS flag is raised by the ADC data being ready. However,

this DAC load position can be advanced before this time by

modifying the contents of the DAC advance field in Control

31 increments of weight 1/(FS × 32), as shown in Table 15.

The sample rate, fS, depends on the setting of both the MCLK

divider and the sample rate divider, as shown in Table 12 and

Table 14. In certain circumstances this DAC update adjustment

can reduce the group delay when the ADC and DAC are used to

process data in series. For more information about how the

DAC advance register can be used, see the section Configuring

an AD73322L to Operate in Mixed Mode.

NOTE: The DAC advance register should not be changed while

the DAC section is powered up.

Table 15. DAC Timing Control

DA4

DA3

DA2

DA1

DA0

Time Advance

0 s

1/(FS × 32) s

2/(FS × 32) s

30/(FS × 32) s

31/(FS × 32) s

Table 16. Control Register Map

Address (Binary)

Name

Description

Type

Width

Reset Setting (Hex)

000

CRA

Control Register A

R/W

0x00

001

CRB

Control Register B

R/W

0x00

010

CRC

Control Register C

R/W

0x00

011

CRD

Control Register D

R/W

0x00

100

CRE

Control Register E

R/W

0x00

101

CRF

Control Register F

R/W

0x00

110

CRG

Control Register G

R/W

0x00

111

CRH

Control Register H

R/W

0x00

Table 17. Control Word Description

C/D

R/W

Device Address

Control

Frame

Description

Bit 15

Control/Data

When set high, this bit signifies a control word in program or mixed program/data modes. When set

low, it signifies a data-word in mixed program/data mode or an invalid control word in program mode.

Bit 14

Read/Write

When set low, this bit tells the device that the data field is to be written to the register selected by the

selected register is to be written to the data field in the input serial register and that the new control

word is to be output from the device via the serial output.

Bits 13 to 11

Device Address

This 3-bit field holds the address information. Only when this field is zero is a device selected. If the

address is not zero, it is decremented and the control word is passed out of the device via the serial

output.

Bits 10 to 8

This 3-bit field is used to select one of the eight control registers on the AD73322L.

Bits 7 to 0

This 8-bit field holds the data that is to be written to or read from the selected register provided the

address field is zero.

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