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TUSB1046AI-DCI датащи(PDF) 21 Page - Texas Instruments

номер детали TUSB1046AI-DCI
подробное описание детали  USB Type-C DisplayPort ALT Mode 10-Gbps Linear Redriver Crosspoint Switch
PDF  48 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

TUSB1046AI-DCI датащи(HTML) 21 Page - Texas Instruments

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background image
T
d_pg
VCC
Internal
Power
Good
T Cfg_su
TCfg_hd
DISABLED
USB3.1- only
FLIP = 0
If (( CTL[1:0 ] ==2'b 00 | CTL[1:0 ] ==2'b 01 ) & FLIP == 0 ) {
USB3.1- only no FLIP;
} ELSEIF((CTL[1:0 ] ==2'b 00 | CTL[1:0 ] ==2'b01 ) & FLIP == 1 ){
USB3.1- only with FLIP ;
} ELSEIF(CTL[1:0 ] ==2'b 10 & FLIP ==0 ) {
4-Lane DP no FLIP;
} ELSEIF(CTL[1:0 ] ==2'b 10 & FLIP ==1 ){
4-Lane DP with FLIP ;
} ELSEIF(CTL[1:0 ] ==2'b 11 & FLIP ==0 ) {
2-Lane DP USB3.1 no FLIP;
} ELSE{
2-Lane DP USB3.1 with FLIP ;
};
CTL[1:0 ] pins
FLIP pin
CFG pins
In GPIO mode
DISABLED
USB3.1- only
FLIP = 0
TUSB1046A-DCI
In I2C mode
Mode of operation
determined by value of
FLIPSEL bit and CTLSEL[1:0]
bits at offset0x0A. Default
is USB3.1- only no Flip.
Tctl_db
V
CC (min)
TUSB1046A-DCI
21
TUSB1046A-DCI
www.ti.com
SLLSF13 – JUNE 2017
Product Folder Links: TUSB1046A-DCI
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
(1)
Following pins comprise CFG pins: I2C_EN, EQ[1:0], SSEQ[1:0], and DPEQ[1:0].
(2)
Recommend CFG pins are stable when VCC is at min.
8.4.6 Operation Timing – Power Up
Figure 18. Power-Up Timing
Table 8. Power-Up Timing(1)(2)
PARAMETER
MIN
MAX
UNIT
td_pg
VCC (minimum) to Internal Power Good asserted high
500
µs
tcfg_su
CFG(1) pins setup(2)
250
µs
tcfg_hd
CFG(1) pins hold
10
µs
tCTL_DB
CTL[1:0] and FLIP pin debounce
16
ms
tVCC_RAMP
VCC supply ramp requirement
100
ms



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