Philips Semiconductors

Product specification

SCN2652/SCN68652

Multi-protocol communications controller (MPCC)

1995 May 01

6

M

U

X

RxSI

FROM

XMITTER

MM

SEL

SYNC

FF

CCSR (8)

COMPARATOR

HSR (16)

8

8

M

U

X

RxSR (8)

TO

RDSRL

ZERO (BOP)

DELETION

LOGIC

ZERO

DELETION

CONTROL

PARITY (BCP)

LOGIC

M

U

X

BCP

BOP

RxCRC ACC

CRC–16 (BCP) OR

CCRC–CCITT

(BOP)

CRC–16 = 0

COMPARATOR

CRC–CCIT = F0B8

RERR

RECEIVER

CONTROL

LOGIC

RxC

NOTES:

1.

Detected in SYNC FF and 7 MS bits of CCSR.

2.

In BOP mode, a minimum of two data characters must be received to turn the receiver active.

RESET

RxE

RxA

RxDA

RxSA

S/F

1-BIT

DELAY

SD00060

Figure 4. MPCC Receiver Data Path

TXSR (8)

M

U

X

BOP

ZERO

INSERTION

LOGIC

ZERO

INSERTION

CONTROL

TRANS-

MITTER

CONTROL

LOGIC

TxC

NOTES:

1.

TxCRC selected if TEOM = 1 and the last data character has been shifted out of TxSR.

2.

In BCP parity selected will be generated after each character is shifted out of TxSR.

RESET

TxE

TxA

TxBE

TxU

SD00088

TXCRC ACC (16)

CRC–16 OR CRC–CCITT

CONTROL

CHARACTER

GENERATOR

BCP

PARITY

GENERATION

FLAG

ABORT

GA

SYNC

FF

1 BIT

DELAY

FROM

TxSO

Figure 5. MPCC Transmitter Data Path