SHINDENGEN

ELECTRIC MFG.CO.,LTD

- 17 -

2.9

Application circuit

2.9.1 Slave stop protection

Master

Slave

The TIMER and LATCH pins of the slave IC and the COMP pin of the master IC can be used to

keep the master IC from operating independently while the slave IC is not working due to an

external problem. For example, if the interleaving signal wire is disconnected.

Fig. 20 shows an example of a 3-phase connection circuit. Fig. 21 shows the circuit operating

sequence.

As shown in Fig. 20, the control coil of each choke coil is connected to the TIMER and LATCH

pins of the slave IC and the COMP pin of the master IC. See Fig. 20 for the structure and polarity

of each choke coil.

During normal operations, the TIMER pin voltage is kept near 0 V by charging and discharging

each control coil. The LATCH pin is in a low impedance state (GND level).

If a slave IC fails to function due to a problem, the TIMER pin voltage increases. When the

voltage reaches 2.5 V, the LATCH pin enters and remains in a high impedance state (open

collector). This activates the transistor connected between the COMP and GND pins of the

master IC and halts the oscillation of the master IC.

The LATCH pin is unlatched when VCC is reduced to 7.5 V or less. If you do not intend to use this

function, short-circuit the TIMER pin and the GND.

During certain periods, only the master IC operates while the slave IC does not—for instance,

when the output overvoltage protection (OVP) is on at startup. In this case, the TIMER pin is

discharged by the switch in the slave IC to 0 V.

As soon as the OVP is released, the slave IC stops discharging the TIMER pin. See Section

2.8.2 for more information on output overvoltage protection (OVP).

～

～

＋

ー

Master

IC

Slave IC

(1)

Slave IC

(2)

COMP

Vcc

LATCH

(S1)

TIMER

(S1)

Vcc

LATCH

(S2)

TIMER

(S2)

1000p

22k

22k

56k

56k

56k

1u

1u

56k

1k

Fig. 20 Examples of circuit configurations that protect against problems with the slave