ADAU1772BCPZ-R7 datasheet(106/117 Pages) AD

номер детали	ADAU1772BCPZ-R7

подробное описание детали	Four ADC, Two DAC Low Power Codec

PDF	117 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

Logo

106 / 117 page

Data Sheet

ADAU1772

Rev. C | Page 105 of 116

DECIMATOR POWER CONTROL REGISTER

Address: 0x0044, Reset: 0x00, Name: DECIM_PWR_MODES

These bits enable clocks to the digital filters and ASRC decimator filters of the ADCs. These bits must be enabled for all channels that will be used

in the design. To use the ADCs, these SINC_x_EN bits must be enabled along with the appropriate ADC_x_EN bits in the ADC_CONTROL2

and ADC_CONTROL3 registers. If the digital microphone inputs are used, the SINC_x_EN bits can be set without setting ADC_x_EN.

Table 95. Bit Descriptions for DECIM_PWR_MODES

Bits

Bit Name

Settings

Description

Reset

Access

DEC_3_EN

Control power to the ASRC3 decimator.

0x0

Powered down

Powered up

DEC_2_EN

Control power to the ASRC2 decimator.

0x0

Powered down

Powered up

DEC_1_EN

Control power to the ASRC1 decimator.

0x0

Powered down

Powered up

DEC_0_EN

Control power to the ASRC0 decimator.

0x0

Powered down

Powered up

SINC_3_EN

ADC3 filter power control.

0x0

Powered down

Powered up

SINC_2_EN

ADC2 filter power control.

0x0

Powered down

Powered up

SINC_1_EN

ADC1 filter power control.

0x0

Powered down

Powered up

SINC_0_EN

ADC0 filter power control.

0x0

Powered down

Powered up

ADAU1772BCPZ-R7 датащи(PDF) 106 Page - Analog Devices

ADAU1772BCPZ-R7 датащи(HTML) 106 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL