ADAU1772BCPZ-R7 datasheet(54/117 Pages) AD

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Data Sheet

ADAU1772

Rev. C | Page 53 of 116

CLOCK CONTROL REGISTER

Address: 0x0000, Reset: 0x00, Name: CLK_CONTROL

This register is used to enable the internal clocks.

Table 30. Bit Descriptions for CLK_CONTROL

Bits

Bit Name

Settings

Description

Reset

Access

PLL_EN

Enable PLL. When this bit is set to 0, the PLL is powered down and the PLL

output clock is disabled. The PLL should not be enabled until after all the

PLL control settings (Register PLL_CTRL0 to Register PLL_CTRL5) have been

set. The PLL clock output is active when both PLL_EN = 1 and COREN = 1.

0x0

PLL disabled

PLL enabled

SPK_FLT_DIS

Disable I2C spike filter. By default, the SDA and SCL inputs have a 50 ns

spike suppression filter. When the control interface is in SPI mode, this

filter is disabled regardless of this setting.

0x0

I2C spike filter enabled

I2C spike filter disabled

XTAL_DIS

Disable crystal oscillator.

0x0

Crystal oscillator enabled

Crystal oscillator disabled

CLKSRC

Main clock source.

0x0

External pin drives main clock.

PLL drives main clock. This bit should only be set after LOCK in

CC_CDIV

SCLK divider control. The core clock (SCLK) is used only by the core. It

must run at 12.288 MHz.

0x0

Div 2: divide PLL/external clock by 2

Div 1: divide PLL/external clock by 1

CC_MDIV

MCLK divider control. The internal master clock (MCLK) of the IC is used by

all digital logic except the core. It must run at 12.288 MHz.

0x0

Div 2: divide PLL/external clock by 2

Div 1: divide PLL/external clock by 1

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