ADAU1361BCPZ-R7 datasheet(26/81 Pages) AD

номер детали	ADAU1361BCPZ-R7

подробное описание детали	Audio Codec with Integrated PLL

PDF	81 Pages

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производитель	AD [Analog Devices]

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ADAU1361

Rev. C | Page 25 of 80

Case 2: PLL Is Used

The core clock to the entire chip is off during the PLL lock

acquisition period. The user can poll the lock bit to determine

when the PLL has locked. After lock is acquired, the ADAU1361

can be started by asserting the core clock enable bit (COREN)

in Register R0 (clock control register, Address 0x4000). This bit

enables the core clock to all the internal blocks of the ADAU1361.

PLL Lock Acquisition

During the lock acquisition period, only Register R0 (Address

0x4000) and Register R1 (Address 0x4002) are accessible through

the control port. Because all other registers require a valid master

clock for reading and writing, do not attempt to access any other

enable bit (COREN) and the lock bit are both asserted.

To program the PLL during initialization or reconfiguration of

the clock setting, the following procedure must be followed:

Power down the PLL.

Reset the PLL control register.

Start the PLL.

Poll the lock bit.

Assert the core clock enable bit after the PLL lock

is acquired.

The PLL control register (Register R1, Address 0x4002) is a

48-bit register where all bits must be written with a single

continuous write to the control port.

ADAU1361BCPZ-R7 датащи(PDF) 26 Page - Analog Devices