AD9280-EB datasheet(15/25 Pages) AD

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AD9280

–14–

DRIVING THE ANALOG INPUT

Figure 25 shows the equivalent analog input of the AD9280, a

sample-and-hold amplifier (switched capacitor input SHA).

Bringing CLK to a logic low level closes Switches 1 and 2 and

opens Switch 3. The input source connected to AIN must

charge capacitor CH during this time. When CLK transitions

from logic “low” to logic “high,” Switches 1 and 2 open, placing

the SHA in hold mode. Switch 3 then closes, forcing the output

of the op amp to equal the voltage stored on CH. When CLK

transitions from logic “high” to logic “low,” Switch 3 opens

first. Switches 1 and 2 close, placing the SHA in track mode.

The structure of the input SHA places certain requirements on

the input drive source. The combination of the pin capacitance,

CP, and the hold capacitance, CH, is typically less than 5 pF.

The input source must be able to charge or discharge this ca-

pacitance to 8-bit accuracy in one half of a clock cycle. When

the SHA goes into track mode, the input source must charge or

discharge capacitor CH from the voltage already stored on CH

to the new voltage. In the worst case, a full-scale voltage step on

the input, the input source must provide the charging current

through the RON (50 Ω) of Switch 1 and quickly (within 1/2 CLK

period) settle. This situation corresponds to driving a low input

impedance. On the other hand, when the source voltage equals

the value previously stored on CH, the hold capacitor requires

no input current and the equivalent input impedance is ex-

tremely high.

Adding series resistance between the output of the source and

the AIN pin reduces the drive requirements placed on the

source. Figure 26 shows this configuration. The bandwidth of

the particular application limits the size of this resistor. To

maintain the performance outlined in the data sheet specifica-

tions, the resistor should be limited to 20

Ω or less. For applica-

tions with signal bandwidths less than 16 MHz, the user may

proportionally increase the size of the series resistor. Alterna-

tively, adding a shunt capacitance between the AIN pin and

analog ground can lower the ac load impedance. The value of

this capacitance will depend on the source resistance and the

required signal bandwidth.

The input span of the AD9280 is a function of the reference

voltages. For more information regarding the input range, see

the Internal and External Reference sections of the data sheet.

AIN

(REFTS

REFBS)

SHA

AD9280

Figure 25. AD9280 Equivalent Input Structure

AIN

< 20

AD9280

Figure 26. Simple AD9280 Drive Configuration

In many cases, particularly in single-supply operation, ac cou-

pling offers a convenient way of biasing the analog input signal

at the proper signal range. Figure 27 shows a typical configura-

tion for ac-coupling the analog input signal to the AD9280.

Maintaining the specifications outlined in the data sheet

requires careful selection of the component values. The most

important is the f–3 dB high-pass corner frequency. It is a function of

R2 and the parallel combination of C1 and C2. The f–3 dB point

can be approximated by the equation:

f–3 dB = 1/(2

× pi × [R2] CEQ)

where CEQ is the parallel combination of C1 and C2. Note that

C1 is typically a large electrolytic or tantalum capacitor that

becomes inductive at high frequencies. Adding a small ceramic

or polystyrene capacitor (on the order of 0.01

µF) that does not

become inductive until negligibly higher frequencies, maintains

a low impedance over a wide frequency range.

NOTE: AC coupled input signals may also be shifted to a desired

level with the AD9280’s internal clamp. See Clamp Operation.

AIN

AD9280

VBIAS

VIN

Figure 27. AC Coupled Input

There are additional considerations when choosing the resistor

values. The ac-coupling capacitors integrate the switching tran-

sients present at the input of the AD9280 and cause a net dc

bias current, IB, to flow into the input. The magnitude of the

bias current increases as the signal magnitude deviates from

V midscale and the clock frequency increases; i.e., minimum

bias current flow when AIN = V midscale. This bias current

will result in an offset error of (R1 + R2)

× IB. If it is necessary

to compensate this error, consider making R2 negligibly small or

modifying VBIAS to account for the resultant offset.

In systems that must use dc coupling, use an op amp to level-

shift a ground-referenced signal to comply with the input re-

quirements of the AD9280. Figure 28 shows an AD8041 config-

ured in noninverting mode.

AIN

AD9280

0.1 F

+VCC

MIDSCALE

OFFSET

VOLTAGE

0VDC 1V p-p

AD8041

Figure 28. Bipolar Level Shift

REV. E

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