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AD9225

Table V. Out-of-Range Truth Table

OTR

MSB

Analog Input Is

In Range

Underrange

Overrange

OVER = “1”

UNDER = “1”

MSB

OTR

MSB

Figure 23. Overrange or Underrange Logic

Digital Output Driver Considerations (DRVDD)

The AD9225 output drivers can be configured to interface with

5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V,

respectively. The output drivers are sized to provide sufficient

output current to drive a wide variety of logic families. However,

large drive currents tend to cause glitches on the supplies and may

affect SINAD performance. Applications requiring the ADC to

drive large capacitive loads or large fanout may require additional

decoupling capacitors on DRVDD. In extreme cases, external

buffers or latches may be required.

Clock Input and Considerations

The AD9225 internal timing uses the two edges of the clock input

to generate a variety of internal timing signals. The clock input

must meet or exceed the minimum specified pulse width high and

low (tCH and tCL) specifications for the given ADC as defined in

the Switching Specifications table to meet the rated performance

specifications. For example, the clock input to the AD9225 operat-

ing at 25 MSPS may have a duty cycle between 45% to 55% to

meet this timing requirement since the minimum specified tCH and

tCL is 18 ns. For low clock rates, the duty cycle may deviate from

this range to the extent that both tCH and tCL are satisfied.

All high speed high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given full-scale input

frequency (fIN) due to only aperture jitter (tA) can be calculated

with the following equation:

SNR

= 20 log10

p f IN tA

In the equation, the rms aperture jitter, tA, represents the root-

sum square of all the jitter sources, which include the clock

input, analog input signal, and ADC aperture jitter specification.

Undersampling applications are particularly sensitive to jitter.

Clock input should be treated as an analog signal in cases where

aperture jitter may affect the dynamic range of the AD9225. Power

supplies for clock drivers should be separated from the ADC out-

put driver supplies to avoid modulating the clock signal with digital

noise. Low jitter crystal controlled oscillators make the best clock

sources. If the clock is generated from another type of source (by

gating, dividing, or other method), it should be retimed by the

original clock at the last step.

The clock input is referred to as the analog supply. Its logic thresh-

old is AVDD/2. If the clock is being generated by 3 V logic, it will

have to be level shifted into 5 V CMOS logic levels. This can also

be accomplished by ac coupling and level-shifting the clock signal.

The AD9225 has a clock tolerance of 5% at 25 MHz. One way to

obtain a 50% duty cycle clock is to divide down a clock of higher

frequency, as shown in Figure 24. This configuration will also

decrease the jitter of the source clock.

+5V

50MHz

25MHz

Figure 24. Divide-by-Two Clock Circuit

In this case, a 50 MHz clock is divided by two to produce the

25 MHz clock input for the AD9225. In this configuration, the

duty cycle of the 50 MHz clock is irrelevant.

The input circuitry for the CLOCK pin is designed to accommo-

date CMOS inputs. The quality of the logic input, particularly

the rising edge, is critical in realizing the best possible jitter

performance of the part; the faster the rising edge, the better

the jitter performance.

As a result, careful selection of the logic family for the clock driver,

as well as the fanout and capacitive load on the clock line, is impor-

tant. Jitter-induced errors become more predominant at higher

frequency and large amplitude inputs, where the input slew rate

is greatest.

Most of the power dissipated by the AD9225 is from the analog

power supplies. However, lower clock speeds will reduce digital

current. Figure 25 shows the relationship between power and

clock rate.

SAMPLE RATE

380

360

340

320

300

035

280

260

240

220

200

180

INTERNAL

REFERENCE

INTERNAL

REFERENCE

Figure 25. Power Consumption vs. Clock Rate

Direct IF Down Conversion Using the AD9225

Sampling IF signals above an ADC’s baseband region (i.e.,

dc to fS/2) is becoming increasingly popular in communication

applications. This process is often referred to as direct IF down

conversion or undersampling. There are several potential benefits

in using the ADC to alias (i.e., or mix) down a narrowband or

wideband IF signal. First and foremost is the elimination of a

complete mixer stage with its associated baseband amplifiers and

filters, reducing cost and power dissipation. Second is the ability to

apply various DSP techniques to perform such functions as filter-

ing, channel selection, quadrature demodulation, data reduction,

Rev. C

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