AD9203 datasheet(13/29 Pages) AD

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AD9203

Rev. B | Page 12 of 28

INPUT AND REFERENCE OVERVIEW

Like the voltage applied to the top of the resistor ladder in a

flash A/D converter, the value VREF defines the maximum

input voltage to the A/D core. The minimum input voltage to

the A/D core is automatically defined to be −VREF.

The addition of a differential input structure gives the user an

additional level of flexibility that is not possible with traditional

flash converters. The input stage allows the user to easily

configure the inputs for either single-ended operation or

differential operation. The A/D’s input structure allows the dc

offset of the input signal to be varied independently of the input

span of the converter. Specifically, the input to the A/D core is

the difference of the voltages applied at the AINP and AINN

input pins. Therefore, the equation,

VCORE = AINP − AINN

(1)

defines the output of the differential input stage and provides

the input to the A/D core.

The voltage, VCORE, must satisfy the condition,

−VREF ≤ VCORE ≤ VREF

(2)

where VREF is the voltage at the VREF pin.

The actual span (AINP − AINN) of the ADC is ±VREF.

While an infinite combination of AINP and AINN inputs exist

that satisfy Equation 2, an additional limitation is placed on the

inputs by the power supply voltages of the AD9203. The power

supplies bound the valid operating range for AINP and AINN.

The condition,

AVSS − 0.3 V < AINP < AVDD + 0.3 V

AVSS − 0.3 V < AINN < AVDD + 0.3 V

(3)

where AVSS is nominally 0 V and AVDD is nominally 3 V,

defines this requirement. The range of valid inputs for AINP

and AINN is any combination that satisfies both Equations 2

and 3.

INTERNAL REFERENCE CONNECTION

A comparator within the AD9203 will detect the potential of

the VREF pin. If REFSENSE is grounded, the reference

amplifier switch will connect to the resistor divider (see Figure

19). That will make VREF equal to 1 V. If resistors are placed

between VREF, REFSENSE and ground, the switch will be

connected to the REFSENSE position and the reference

amplitude will depend on the external programming resistors

(Figure 21). If REFSENSE is tied to VREF, the switch will also

connect to REFSENSE and the reference voltage will be 0.5 V

(Figure 20). REFTF and REFBF will drive the ADC conversion

core and establish its maximum and minimum span. The range

of the ADC will equal twice the voltage at the reference pin for

either an internal or external reference.

Figure 19 illustrates the input configured with a 1 V reference.

This will set the single-ended input of the AD9203 in the 2 V

span (2 × VREF). This example shows the AINN input is tied to

the 1 V VREF. This will configure the AD9203 to accept a 2 V

input centered around 1 V.

ADC

CORE

–

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

AINP

AINN

VREF

0.5V

REFTF

REFBF

REFSENSE

AD9203

LOGIC

Figure 19. Internal Reference Set for a 2 V Span

Figure 20 illustrates the input configured with a 0.5 V reference.

This will set the single-ended input of the ADC in a 1 V span

(2 × VREF). The AINN input is tied to the 0.5 VREF. This will

configure the AD9203 to accept a 1 V input centered around

0.5 V.

ADC

CORE

–

LOGIC

AINP

AINN

VREF

0.5V

REFTF

REFBF

REFSENSE

1.75V

1.25V

AD9203

0.1

µF

0.1

µF

0.1

µF

0.1

µF

Figure 20. Internal Reference Set for a 1 V Span

Figure 21 shows the reference programmed by external resistors

for 0.75 V. This will set the ADC to receive a 1.5 V span

centered about 0.75 V. The reference is programmed according

to the algorithm:

VREF = 0.5 V × [1 + (RA/RB)]

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