LTC3421

8

3421f

OPERATIO

LOW VOLTAGE START-UP

The LTC3421 includes an independent start-up oscillator

designed to start-up at input voltages of 0.85V typical. The

frequency and peak current limit during start-up are inter-

nally controlled. The device can start-up under some load

(see graph of Start-Up Current vs Input Voltage). Soft-

start and inrush current limiting are provided during start-

up as well as normal mode. The same soft-start capacitor

is used for each operating mode.

normal operating mode. Once the output voltage exceeds

ment for a large input capacitor. The input voltage can drop

as low as 0.5V without affecting circuit operation. The

limiting factor for the application becomes the availability

of the power source to supply sufficient energy to the

output at the low voltages and the maximum duty cycle,

which is clamped at 91% typical.

LOW NOISE FIXED FREQUENCY OPERATION

Shutdown

The part is shut down by pulling SHDN below 0.3V, and

activated by pulling the pin initially above 1V and maintain-

ing a high state down to 0.5V. Note that the SHDN pin can

than the absolute maximum rating.

Soft-Start

The soft-start time is programmed with an external capaci-

tor to ground on the SS pin. An internal current source

charges it with a nominal 2.5

µA. The voltage on the SS pin

is used to control the peak current limit until the voltage on

the capacitor exceeds 1.6V, at which point the external

resistor sets the peak current. In the event of a com-

manded shutdown or a thermal shutdown, the capacitor is

discharged automatically. Note that Burst Mode operation

is inhibited during the soft-start time.

Oscillator

The frequency of operation is set through a resistor from

tor resides inside the IC. The oscillator can be synchro-

nized with an external clock applied to the SYNC pin. When

synchronizing the oscillator, the free running frequency

must be set to an approximately 30% lower frequency

than the desired synchronized frequency.

Current Sensing

Lossless current sensing converts the peak current signal

to a voltage to sum in with the internal slope compensa-

tion. This summed signal is compared to the error ampli-

fier output to provide a peak current control command for

the PWM. The slope compensation in the IC is adaptive to

the input voltage and output voltage. Therefore, the con-

verter provides the proper amount of slope compensation

to ensure stability, but not an excess to cause a loss of

phase margin in the converter.

Error Amplifier

The error amplifier is a transconductance amplifier, with

its positive input internally connected to the 1.22V refer-

ence and its negative input connected to FB. A simple

compensation network is placed from COMP to ground.

Internal clamps limit the minimum and maximum error

amplifier output voltage for improved large-signal tran-

sient response. During sleep (in Burst Mode operation),

the compensation pin is high impedance; however, clamps

limit the voltage on the external compensation network,

preventing the compensation capacitor from discharging

to zero during the sleep time.

Current Limit

The programmable current limit circuit sets the maximum

peak current. This clamp level is programmed with a

current limit is automatically set to a nominal value of 0.6A

peak for optimal efficiency.

I

R

150

where I is in amps and R is in k

Ω.