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AD9433

Rev. A | Page 17 of 20

THEORY OF OPERATION

The AD9433 is a 12-bit pipeline converter that uses a switched-

capacitor architecture. Optimized for high speed, this converter

provides flat dynamic performance up to and beyond the

Nyquist limit. DNL transitional errors are calibrated at final test

to a typical accuracy of 0.25 LSB or less.

ENCODE INPUT

Any high speed ADC is extremely sensitive to the quality of the

sampling clock provided by the user. A track-and-hold circuit is

essentially a mixer, and any noise, distortion, or timing jitter on

the clock is combined with the desired signal at the ADC output.

For this reason, considerable care has been taken in the design

of the encode input of the AD9433, and the user is advised to

give commensurate thought to the clock source.

The AD9433 has an internal clock duty cycle stabilization

circuit that locks to the rising edge of ENCODE (falling edge

of ENCODE if driven differentially) and optimizes timing

internally. This allows for a wide range of input duty cycles at

the input without degrading performance. Jitter in the rising

edge of the input is still of paramount concern and is not

reduced by the internal stabilization circuit. This circuit is

always on and cannot be disabled by the user.

The ENCODE and ENCODE inputs are internally biased

to 3.75 V (nominal) and support either differential or single-

ended signals. For best dynamic performance, a differential

signal is recommended. Good performance is obtained using

an MC10EL16 translator in the circuit to directly drive the

encode inputs (see

Figure 41

PECL

GATE

ENCODE

AD9433

ENCODE

510Ω

Figure 41. Using PECL to Drive the ENCODE Inputs

Often, the cleanest clock source is a crystal oscillator producing

a pure, single-ended sine wave. In this configuration, or with

any roughly symmetrical, single-ended clock source, the signal

can be ac-coupled to the encode input. To minimize jitter, the

signal amplitude should be maximized within the input range

described in Table 7. The 12 kΩ resistors to ground at each of

the inputs, in parallel with the internal bias resistors, set the

common-mode voltage to approximately 2.5 V, allowing the

maximum swing at the input. The ENCODE input should be

bypassed with a capacitor to ground to reduce noise. This ensures

that the internal bias voltage is centered on the encode signal.

For best dynamic performance, impedances at ENCODE and

ENCODE should match.

ENCODE

AD9433

ENCODE

12kΩ

25Ω

50Ω

12kΩ

0.1µF

50Ω

SINE

SOURCE

Figure 42. Single-Ended Sine Source Encode Circuit

Figure 43 shows another preferred method for clocking the

AD9433. The clock source (low jitter) is converted from single-

ended to differential using an RF transformer. The back-to-back

Schottky diodes across the transformer secondary limit clock

excursions into the AD9433 to approximately 0.8 V p-p differ-

ential. This helps to prevent the large voltage swings of the clock

from feeding through to other portions of the AD9433 and limits

the noise presented to the encode inputs. A crystal clock oscilla-

tor can also be used to drive the RF transformer if an appropriate

limiting resistor (typically 100 Ω) is placed in series with the

primary.

ENCODE

AD9433

ENCODE

0.1µF

T1-4T

100Ω

HMS2812

DIODES

CLOCK

SOURCE

Figure 43. Transformer-Coupled Encode Circuit

ENCODE VOLTAGE LEVEL DEFINITION

The voltage level definitions for driving ENCODE and ENCODE

in single-ended and differential mode are shown in

Figure 44

VIHD

VICM, VECM

VILD

ENCODE

VID

VIHS

VICM, VECM

VILS

ENCODE

0.1µF

Figure 44. Differential and Single-Ended Input Levels

Table 7. Encode Inputs

Input

Min

Nominal

Max

Differential Signal Amplitude

(VID)

200 mV

750 mV

5.5 V

Input Voltage Range

(VIHD, VILD, VIHS, VILS)

−0.5 V

VCC + 0.5 V

Internal Common-Mode Bias

(VICM)

3.75 V

External Common-Mode Bias

(VECM)

2.0 V

4.25 V

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