ADC12DL040 datasheet(19/26 Pages) NSC

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Applications Information (Continued)

Where dev is the angular difference in degrees between the

two signals having a 180˚ relative phase relationship to each

other (see Figure 3). Drive the analog inputs with a source

impedance less than 100

Ω.

For differential operation, each analog input pin of the differ-

ential pair should have a peak-to-peak voltage equal to the

reference voltage, V

REF, be 180 degrees out of phase with

each other and be centered around V

CM.

1.3.1 Single-Ended Operation

Performance with differential input signals is better than with

single-ended signals. For this reason, single-ended opera-

tion is not recommended. However, if single ended-operation

is required and the resulting performance degradation is

acceptable, one of the analog inputs should be connected to

the d.c. mid point voltage of the driven input. The peak-to-

peak differential input signal at the driven input pin should be

twice the reference voltage to maximize SNR and SINAD

performance (Figure 2b). For example, set V

REF to 0.5V,

bias V

IN− to 1.0V and drive VIN+ with a signal range of 0.5V

to 1.5V.

Because very large input signal swings can degrade distor-

tion performance, better performance with a single-ended

input can be obtained by reducing the reference voltage

when maintaining a full-range output. Table 1 and Table 2

indicate the input to output relationship of the ADC12DL040.

TABLE 1. Input to Output Relationship – Differential

Input

IN+

IN−

Binary Output

2’s Complement

Output

CM −

REF/2

CM +

REF/2

0000 0000 0000

1000 0000 0000

CM −

REF/4

CM +

REF/4

0100 0000 0000

1100 0000 0000

1000 0000 0000

0000 0000 0000

CM +

REF/4

CM −

REF/4

1100 0000 0000

0100 0000 0000

CM +

REF/2

CM −

REF/2

1111 1111 1111

0111 1111 1111

TABLE 2. Input to Output Relationship – Single-Ended

Input

IN+

IN−

Binary Output

2’s Complement

Output

CM −

REF

0000 0000 0000

1000 0000 0000

CM −

REF/2

0100 0000 0000

1100 0000 0000

1000 0000 0000

0000 0000 0000

CM +

REF/2

1100 0000 0000

0100 0000 0000

CM +

REF

1111 1111 1111

0111 1111 1111

1.3.2 Driving the Analog Inputs

The V

IN+ and the VIN− inputs of the ADC12DL040 consist of

an analog switch followed by a switched-capacitor amplifier.

The capacitance seen at the analog input pins changes with

the clock level, appearing as 8 pF when the clock is low, and

7 pF when the clock is high.

As the internal sampling switch opens and closes, current

pulses occur at the analog input pins, resulting in voltage

spikes at the signal input pins. As a driving amplifier attempts

to counteract these voltage spikes, a damped oscillation

may appear at the ADC analog input. Do not attempt to filter

out these pulses. Rather, use amplifiers to drive the

ADC12DL040 input pins that are able to react to these

pulses and settle before the switch opens and another

sample is taken. The LMH6702 LMH6628, LMH6622 and the

LMH6655 are good amplifiers for driving the ADC12DL040.

To help isolate the pulses at the ADC input from the amplifier

output, use RCs at the inputs, as can be seen in Figure 4

through Figure 6 . These components should be placed

close to the ADC inputs because the input pins of the ADC is

the most sensitive part of the system and this is the last

opportunity to filter that input.

For Nyquist applications the RC pole should be at the ADC

sample rate. The ADC input capacitance in the sample mode

should be considered when setting the RC pole. For wide-

band undersampling applications, the RC pole should be set

at about 1.5 to 2 times the maximum input frequency to

maintain a linear delay response.

A single-ended to differential conversion circuit is shown in

Figure 6. Table 3 gives resistor values for that circuit to

provide input signals in a range of 1.0V ±0.5V at each of the

differential input pins of the ADC12DL040.

TABLE 3. Resistor Values for Circuit of Figure 6

SIGNAL

RANGE

R5, R6

0 - 0.25V

open

Ω

124

Ω 1500Ω 1000Ω

0 - 0.5V

Ω

open

Ω 499Ω 1500Ω 499Ω

±0.25V

100

Ω

698

Ω

100

Ω

698

Ω

499

Ω

1.3.3 Input Common Mode Voltage

The input common mode voltage, V

CM, should be in the

range of 0.5V to 2.0V and be a value such that the peak

excursions of the analog signal does not go more negative

than ground or more positive than 2.6V. See Section 1.2

20100212

FIGURE 3. Angular Errors Between the Two Input

Signals Will Reduce the Output Level or Cause

Distortion

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