AD9444-CMOSSLASHPCB datasheet(12/41 Pages) AD

12 / 41 page

AD9444

Rev. 0 | Page 11 of 40

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode

Pin No.

Mnemonic

Description

1, 8 to 9,

16 to 18,

24 to 27,

34 to 35, 38,

41 to 42, 87,

89 to 95, 98

AVDD1

3.3 V (±5%) Analog Supply.

2 to 4

DNC

Do Not Connect. These pins

should float.

OUTPUT

MODE

CMOS Compatible Output Logic

Mode Control Pin. OUTPUT MODE

= 0 for CMOS mode, and OUTPUT

MODE = 1 (AVDD1) for LVDS

outputs.

DFS

Data Format Select Pin. CMOS

control pin that determines the

format of the output data. DFS =

high (AVDD1) for twos comple-

ment, DFS = low (ground) for

offset binary format.

LVDSBIAS

Set Pin for LVDS Output Current.

Place 3.7 kΩ resistor terminated to

DRGND.

SENSE

Reference Mode Selection.

Connect to AGND for internal 1 V

reference, and connect to AVDD2

for external reference.

VREF

1.0 V Reference I/O—Function

Dependent on SENSE. Decouple

to ground with 0.1 µF and 10 µF

capacitors.

12, 15, 20,

23, 32, 86,

88, 96 to 97,

99, Exposed

Heat Sink

AGND

Analog Ground. The exposed

heat sink on the bottom of the

package must be connected to

AGND.

REFT

Differential Reference Output.

Decoupled to ground with 0.1 µF

capacitor and to REFB (Pin 14) with

0.1 µF and 10 µF capacitors.

REFB

Differential Reference Output.

Decoupled to ground with a 0.1 µF

capacitor and to REFT (Pin 13) with

0.1 µF and 10 µF capacitors.

19, 28 to 31,

39 to 40

AVDD2

5.0 V Analog Supply (±5%).

VIN+

Analog Input—True.

VIN−

Analog Input—Complement.

Internal Bypass Node. Connect a

0.1 µF capacitor from this pin

to AGND.

CLK+

Clock Input—True.

CLK−

Clock Input—Complement.

D0− (LSB)

D0 Complement Output Bit

(LVDS Levels).

Pin No.

Mnemonic

Description

D0+

D0 True Output Bit.

D1−

D1 Complement Output Bit.

D1+

D1 True Output Bit.

47, 54, 62,

75, 83

DRVDD

3.3 V Digital Output Supply

(3.0 V to 3.6 V).

48, 53, 61,

67, 74, 82

DRGND

Digital Ground.

D2−

D2 Complement Output Bit.

D2+

D2 True Output Bit.

D3−

D3 Complement Output Bit.

D3+

D3 True Output Bit.

D4−

D4 Complement Output Bit.

D4+

D4 True Output Bit.

D5−

D5 Complement Output Bit.

D5+

D5 True Output Bit.

D6−

D6 Complement Output Bit.

D6+

D6 True Output Bit.

DCO−

Data Clock Output—Complement.

DCO+

Data Clock Output—True.

D7−

D7 Complement Output Bit.

D7+

D7 True Output Bit.

D8−

D8 Complement Output Bit.

D8+

D8 True Output Bit.

D9−

D9 Complement Output Bit.

D9+

D9 True Output Bit.

D10−

D10 Complement Output Bit.

D10+

D10 True Output Bit.

D11−

D11 Complement Output Bit.

D11+

D11 True Output Bit.

D12−

D12 Complement Output Bit.

D12+

D12 True Output Bit.

D13−

D13 Complement Output.

D13+ (MSB)

D13 True Output Bit.

OR−

Out-of-Range Complement

Output Bit.

OR+

Out-of-Range True Output Bit.

100

DCS MODE

Clock Duty Cycle Stabilizer (DCS)

Control Pin, CMOS-Compatible.

DCS = low (AGND) to enable DCS

(recommended). DCS = high

(AVDD1) to disable DCS.

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