AT40K datasheet(33/67 Pages) ATMEL

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AT40K/AT40KLV Series FPGA

0896C–FPGA–04/02

AC Timing Characteristics – 3.3V Operation AT40KLV

Delays are based on fixed loads and are described in the notes.

Maximum times based on worst case: VCC = 3.00V, temperature = 70°C

Minimum times based on best case: VCC = 3.60V, temperature = 0°C

Maximum delays are the average of tPDLH and tPDHL.

Cell Function

Parameter

Path

-3

Units

Notes

Core

2-input Gate

tPD (Maximum)

x/y -> x/y

2.9

1 unit load

3-input Gate

PD (Maximum)

x/y/z -> x/y

2.8

1 unit load

3-input Gate

PD (Maximum)

x/y/w -> x/y

3.4

1 unit load

4-input Gate

PD (Maximum)

x/y/w/z -> x/y

3.4

1 unit load

Fast Carry

tPD (Maximum)

y -> y

2.3

1 unit load

Fast Carry

tPD (Maximum)

x -> y

2.9

1 unit load

Fast Carry

tPD (Maximum)

y -> x

3.0

1 unit load

Fast Carry

PD (Maximum)

x -> x

2.3

1 unit load

Fast Carry

PD (Maximum)

w -> y

3.4

1 unit load

Fast Carry

PD (Maximum)

w -> x

3.4

1 unit load

Fast Carry

tPD (Maximum)

z -> y

3.4

1 unit load

Fast Carry

tPD (Maximum)

z -> x

2.4

1 unit load

DFF

tPD (Maximum)

q -> x/y

2.8

1 unit load

DFF

PD (Maximum)

R -> x/y

3.2

1 unit load

DFF

PD (Maximum)

S -> x/y

3.0

1 unit load

DFF

PD (Maximum)

q -> w

2.7

Incremental -> L

tPD (Maximum)

x/y -> L

2.4

1 unit load

Local Output Enable

tPZX (Maximum)

oe -> L

2.8

1 unit load

Local Output Enable

tPXZ (Maximum)

oe -> L

2.4

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