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4

Long Term Settling Time

Time (s)

0.4

-0.4

1

µ

1m

1

0

10

µ

100

µ

10m

100m

-0.2

0.2

Closed Loop Output Resistance

Frequency (Hz)

100

0.1

10M

100M

10

1

Gain Flatness & Linear Phase Deviation

Frequency (Hz)

1M

10M

Gain

Phase

Small Signal Pulse Response

Time (10ns/div)

0.20

0.10

-0.20

0

-0.10

Large Signal Pulse Response

Time (10ns/div)

4.0

2.0

-4.0

0

-2.0

Short Term Settling Time

Time (s)

0.2

0.1

-0.2

0

20n

100n

0

-0.1

40n

60n

80n

Temperature (

°C)

7.0

6.0

1.0

-50

0

100

5.0

4.0

3.0

2.0

3.5

3.0

1.5

1.0

0.5

2.5

2.0

50

Settling Time vs. Capacitive Load

CL (F)

70

60

30

20

10

100p

20p

1000p

50

40

60

50

20

10

0

40

30

0.05%

0.1%

CLC408 OPERATION

The CLC408 has a current-feedback (CFB) architecture

built in an advanced complementary bipolar process.

The key features of current-feedback are:

s

AC bandwidth is independent of voltage gain

s

Inherently unity-gain stability

s

Frequency response may be adjusted with

s

High slew rate

s

Low variation in performance for a wide range

of gains, signal levels and loads

s

Fast settling

Current-feedback operation can be explained with a

simple model. The voltage gain for the circuits in Figures 1

and 2 is approximately:

where:

s

s

s

Z(j

ω) is the CLC408’s open-loop

transimpedance gain

s

is the loop gain

The denominator of the equation above is approximately

1

at

low

frequencies.

Near

the

-3dB

corner

the following:

s

Decreases loop gain

s

Decreases bandwidth

s

Reduces gain peaking

s

Lowers pulse response overshoot

s

Affects frequency response phase linearity

V

V

A

1

R

Zj

o

in

v

f

=

Zj

ω

()