CDCU877/CDCU877A

1.8V PHASE LOCK LOOP CLOCK DRIVER

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

6

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

AVDD,

VDDQ

MIN

TYP

MAX

UNIT

VIK

Input (cl inputs)

II = 18 mA

1.7 V

−1.2

V

VOH

High-level output voltage

IOH = −100 µA

1.7 V to

1.9 V

VDDQ

− 0.2

V

VOH

High-level output voltage

IOH = −9 mA

1.7 V

1.1

V

VOL

Low-level output voltage

IOL = 100 µA

0.1

V

VOL

Low-level output voltage

IOL = 9 mA

1.7 V

0.6

V

IO(DL)

Low-level output current, disabled

VO(DL) = 100 mV, OE = L

1.7 V

100

µA

VOD

Differential output voltage (see Note 1)

1.7 V

0.5

V

CK, CK

1.9 V

±250

II

Input current

OE, OS,

FBIN, FBIN

1.9 V

±10

µA

IDD(LD) Supply current, static (IDDQ + IADD)

CK and CK = L

1.9 V

500

µA

IDD

Supply current, dynamic (IDDQ + IADD)

(see Note 2 for CPD calculation)

CK and CK = 270 MHz,

All outputs are open

(not connected to a PCB)

1.9 V

135

mA

IDD

DDQ

ADD

(see Note 2 for CPD calculation)

All outputs are loaded with 2 pF and

120-

Ω termination resistor

1.9 V

235

mA

CI

Input capacitance

CK, CK

VI = VDD or GND

1.8 V

2

3

pF

CI

Input capacitance

FBIN, FBIN

VI = VDD or GND

1.8 V

2

3

pF

CI )

Change in input current

CK, CK

VI = VDD or GND

1.8 V

0.25

pF

CI(∆)

Change in input current

FBIN, FBIN

VI = VDD or GND

1.8 V

0.25

pF

NOTES:

1. VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition.

2. Total IDD =IDDQ +IADD =fCK ×CPD ×VDDQ, solving for CPD = (IDDQ +IADD)/(fCK ×VDDQ) where fCK is the input frequency, VDDQ

is the power supply, and CPD is the power dissipation capacitance.

timing requirements over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fCK

Clock frequency (operating, see Notes 1 and 2)

AVDD, VDD = 1.8 V ±0.1 V

10

400

MHz

fCK

Clock frequency (application, see Notes 1 and 3)

AVDD, VDD = 1.8 V ±0.1 V

160

340

MHz

tDC

Duty cycle, input clock

AVDD, VDD = 1.8 V ±0.1 V

40%

60%

tL

Stabilization time (see Note 4)

AVDD, VDD = 1.8 V ±0.1 V

12

µs

NOTES:

1. The PLL must be able to handle spread spectrum induced skew.

2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other

timing parameters (used for low speed system debug).

3. Application clock frequency indicates a range over which the PLL must meet all timing parameters.

4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal

after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase

lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return

to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle.