REV. B

–14–

AD7910/AD7920

the first SCLK edge the part receives after the falling edge of

CS. This is shown as point A in Figure 11. Although at any

SCLK frequency one dummy cycle is sufficient to power up the

dummy cycle of 16 SCLKs must always elapse to power up the

device up and acquire the input signal. So, if a 5 MHz SCLK

frequency is applied to the ADC, the cycle time will be 3.2 s.

In one dummy cycle, 3.2 s, the part will be powered up and

ms with a 5 MHz SCLK,

only five SCLK cycles will have elapsed. At this stage, the ADC

will be fully powered up and the signal acquired. In this case, the

CS can be brought high after the 10th SCLK falling edge and

When power supplies are first applied to the AD7910/AD7920,

the ADC may power up in either power down mode or in normal

mode. Because of this, it is best to allow a dummy cycle to elapse

to ensure the part is fully powered up before attempting a valid

conversion. Likewise, if the intention is to keep the part in

power-down mode while not in use and the user wishes the part

to power up in power-down mode, the dummy cycle may be

used to ensure the device is in power-down by executing a cycle

such as that shown in Figure 10. Once supplies are applied to

the AD7910/AD7920, the power-up time is the same as that

when powering up from power-down mode. It takes approximately

1

s to power up fully if the part powers up in normal mode. It

is not necessary to wait 1

ms before executing a dummy cycle to

ensure the desired mode of operation. Instead, the dummy

cycle can occur directly after power is supplied to the ADC. If the

first valid conversion is performed directly after the dummy

conversion, care must be taken to ensure that adequate acquisi-

tion time is allowed. As mentioned earlier, when powering up

from the power-down mode, the part will return to track upon

the first SCLK edge applied after the falling edge of

CS. How-

ever when the ADC powers up initially after supplies are

applied, the track-and-hold will already be in track. This means,

assuming one has the facility to monitor the ADC supply cur-

rent, if the ADC powers up in the desired mode of operation and

thus a dummy cycle is not required to change mode, neither is a

dummy cycle required to place the track-and-hold into track.

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7910/AD7920 when

not converting, the average power consumption of the ADC

decreases at lower throughput rates. Figure 12 shows how, as

the throughput rate is reduced, the device remains in its power-

down state longer and the average power consumption over

time drops accordingly.

For example, if the AD7910/AD7920 is operated in a continuous

sampling mode with a throughput rate of 100 kSPS and an SCLK

down mode between conversions, the power consumption is

calculated as follows:

The power dissipation includes the power dissipated while the part

is entering power-down mode, the power dissipated during the

dummy conversion (when the part is exiting power-down mode

and powering up), and the power dissipated during conversion.

As mentioned in the power-down mode section, to enter power-

down mode,

CS has to be brought high anywhere between the

second and 10th SCLK falling edge. Therefore, the power con-

sumption when entering power-down mode will vary depending

on the number of SCLK cycles used. In this example, five SCLK

cycles will be used to enter power-down mode. This gives a time

period of 5

The power-up time is 1

s, which implies that only five SCLK

cycles are required to power up the part. However,

CS has to

remain low until at least the 10th SCLK falling edge when

exiting power-down mode. This means that a minimum of nine

SCLK cycles have to be used to exit power-down mode and

power up the part.

So, if nine SCLK cycles are used, the time to power up the part

and exit power-down mode is 9

Finally, the conversion time is 16

Therefore, the AD7910/AD7920 can be said to dissipate 15 mW

for 3.2 s + 1.8 s + 1 s = 6 s during each conversion cycle. If

the throughput rate is 100 kSPS, the cycle time is 10 s and the

average power dissipated during each cycle is (6/10)

(15 mW) =

9 mW. The power dissipation when the part is in power-down has

not been taken into account as the shutdown current is so low and

it does not have any effect on the overall power dissipation value.

down mode between conversions, the power dissipation during

normal operation is 4.2 mW. Assuming the same timing condi-

tions as before, the AD7910/AD7920 can now be said to

dissipate 4.2 mW for 6

ms during each conversion cycle. With a

throughput rate of 100 kSPS, the average power dissipated during

each cycle is (6/10)

(4.2 mW) = 2.52 mW. Figure 12 shows the

power versus throughput rate when using the power-down mode

between conversions with both 5 V and 3 V supplies.

Power-down mode is intended for use with throughput rates of

approximately 160 kSPS and under, because at higher sampling

rates there is no power saving made by using the power-down mode.

THROUGHPUT RATE (kSPS)

100

0.1

0

10

1

0.01

20

40

60

80

100

120

140

160

180

Figure 12. Power vs. Throughput Rate