80960JD datasheet(11/78 Pages) INTEL

11 / 78 page

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

2.5

Instruction Set Summary

The 80960Jx adds several new instructions to the i960 core architecture. The new instructions are:

• Conditional Move

• Conditional Add

• Conditional Subtract

• Byte Swap

• Halt

• Cache Control

• Interrupt Control

Table 1 identifies the instructions that the 80960Jx supports. Refer to the i960® Jx Microprocessor

Developer’s Manual (272483) for a detailed description of each instruction.

2.6

Faults and Debugging

The 80960Jx employs a comprehensive fault model. The processor responds to faults by making

implicit calls to a fault handling routine. Specific information collected for each fault allows the

fault handler to diagnose exceptions and recover appropriately.

The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to

detect as many as seven different trace event types. Alternatively, mark and fmark instructions

can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are

also available to trap on execution and data addresses.

2.7

Low Power Operation

Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s

sub-micron topology provides the circuit density for optimal cache size and high operating speeds

while dissipating modest power. The processor also uses dynamic power management to turn off

clocks to unused circuits.

Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,

the processor core stops completely while the integrated peripherals continue to function, reducing

overall power requirements up to 90 percent. Processor execution resumes from internally or

externally generated interrupts.

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