AD9689 datasheet(52/134 Pages) AD

52 / 134 page

AD9689

Data Sheet

Rev. A | Page 52 of 134

GPIO Level Control Mode

The GPIO pins determine the exact NCO channel selected.

The following procedure must be followed to use GPIO level

control for NCO channel selection:

1. Configure one or more GPIO pins as NCO channel

selection inputs. GPIO pins not configured as NCO

channel selection are internally tied low.

a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to

0x6 and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to

0x6 and Bits [7:4] in Register 0x0041 to 0x0.

2. Configure the NCO channel selector in GPIO level control

mode by setting Bits[7:4] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

desired GPIO pin ordering.

3. Select the desired NCO channel through the GPIO pins.

GPIO Edge Control Mode

A low to high transition on a single GPIO pin determines the

exact NCO channel selected. The internal channel selection

counter is reset by either SYSREF± or the DDC soft reset.

The following procedure must be followed to use GPIO edge

control for NCO channel selection:

1. Configure one or more GPIO pins as NCO channel

selection inputs.

a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to

0x6 and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to

0x6 and Bits[7:4] in Register 0x0041 to 0x0.

2. Configure the NCO channel selector in GPIO edge control

mode by setting Bits[7:4] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

desired GPIO pin.

3. Configure the wrap point for the NCO channel selection

by setting Bits[3:0] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

to wrap at Channel 4 (0, 1, 2, 3, 4, 0, 1, 2, 3, 4, and so on).

4. Transition the selected GPIO pin from low to high to

increment the NCO channel selection.

NCO channel selection is controlled directly through the

Figure 115 shows an example use case for coherent mode using

three NCO channels. In this example, NCO Channel 0 is actively

downconverting Bandwidth 0 (B0), while NCO Channel 1 and

Channel 2 are in standby mode and are tuned to Bandwidth 1

and Bandwidth 2 (B1 and B2), respectively.

The phase coherent NCO switching feature allows an infinite

number of frequency hops that are all phase coherent. The

initial phase of the NCO is established at time, t0, from

SYSREF± synchronization. Switching the NCO FTW does not

affect the phase. With this feature, only one FTW is required,

but all 16 channels can be used to queue the next hop.

After SYSREF± synchronization at startup, all NCOs across

multiple chips are inherently synchronized.

fS/2

NCO CHANNEL 0

CARRIER FREQUENCY 0

(ACTIVE)

NCO CHANNEL 1

CARRIER FREQUENCY 1

(STANDBY)

NCO CHANNEL 2

CARRIER FREQUENCY 2

(STANDBY)

ACTIVE

DDC

Figure 115. NCO Coherent Mode with Three NCO Channels (B0 Selected)

AD9689 датащи(PDF) 52 Page - Analog Devices

AD9689 датащи(HTML) 52 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL