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AD9642

Data Sheet

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the

chip configuration registers (Address 0x00 to Address 0x02); the

transfer register (Address 0xFF); and the ADC functions registers,

including setup, control, and test (Address 0x08 to Address 0x20).

The memory map register table (Table 13) documents the

default hexadecimal value for each hexadecimal address shown.

The Bit 7 (MSB) column is the start of the default hexadecimal

value given. For example, Address 0x14, the output mode register,

has a hexadecimal default value of 0x01. This means that Bit 0 = 1

and the remaining bits are 0s. This setting is the default output

format value, which is twos complement. For more information

on this function and others, see the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI. This document details

the functions controlled by Register 0x00 to Register 0x20.

Open Locations

All address and bit locations that are not included in Table 13 are

not currently supported for this device. Write 0s to unused bits

of a valid address location. Writing to these locations is required

only when part of an address location is open (for example,

Address 0x18). If the entire address location is open (for example,

Address 0x13), this address location should not be written.

Default Values

After the AD9642 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table (Table 13).

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 to Address 0x20 are shadowed. Writes to these

addresses do not affect part operation until a transfer command

is issued by writing 0x01 to Address 0xFF, setting the transfer

bit. This allows these registers to be updated internally and

simultaneously when the transfer bit is set. The internal update

takes place when the transfer bit is set, and then the bit autoclears.

Rev. B | Page 24 of 28

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