AD9484 datasheet(18/25 Pages) AD

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AD9484

Rev. A | Page 17 of 24

differential output traces be kept close together and at equal

lengths.

An example of the LVDS output using the ANSI standard (default)

data eye and a time interval error (TIE) jitter histogram with

trace lengths less than 24 inches on regular FR-4 material is

shown in Figure 36. Figure 37 shows an example of when the

trace lengths exceed 24 inches on regular FR-4 material. Notice

that the TIE jitter histogram reflects the decrease of the data eye

opening as the edge deviates from the ideal position. It is up to

the user to determine if the waveforms meet the timing budget

of the design when the trace lengths exceed 24 inches.

500

–500

–400

–300

–200

–100

100

200

300

400

–3

–2

–1

TIME (ns)

–40

–20

TIME (ps)

Figure 36. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less

Than 24 Inches on Standard FR-4

600

–600

–400

–200

200

400

–3

–2

–1

0123

TIME (ns)

–100

100

TIME (ps)

Figure 37. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths

Greater Than 24 Inches on Standard FR-4

The format of the output data is offset binary by default. An

example of the output coding format can be found in Table 11.

If it is desired to change the output data format to twos comple-

ment, see the AD9484 Configuration Using the SPI section.

An output clock signal is provided to assist in capturing data

from the AD9484. The DCO is used to clock the output data

and is equal to the sampling clock (CLK) rate. In single data

rate mode (SDR), data is clocked out of the AD9484 and must

be captured on the rising edge of the DCO. See the timing

diagram shown in Figure 2 for more information.

Output Data Rate and Pinout Configuration

The output data of the AD9484 can be configured to drive

12 pairs of LVDS outputs at the same rate as the input clock

signal (SDR mode).

Out-of-Range (OR)

An out-of-range condition exists when the analog input voltage

is beyond the input range of the ADC. OR+ and OR− (OR±)

are digital outputs that are updated along with the data output

corresponding to the particular sampled input voltage. Thus,

OR± has the same pipeline latency as the digital data. OR± is

low when the analog input voltage is within the analog input

range and high when the analog input voltage exceeds the input

range, as shown in Figure 38. OR± remains high until the analog

input returns to within the input range and another conversion

is completed. By logically AND’ing OR± with the MSB and its

complement, overrange high or underrange low conditions can

be detected.

OR± DATA OUTPUTS

OR±

+FS – 1 LSB

+FS – 1/2 LSB

+FS

–FS

–FS + 1/2 LSB

–FS – 1/2 LSB

1111

0000

1111

1110

0001

0000

Figure 38. OR± Relation to Input Voltage and Output Data

TIMING

The AD9484 provides latched data outputs with a pipeline delay

of 15 clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines and loads placed

on them to reduce transients within the AD9484. These transi-

ents can degrade the dynamic performance of the converter.

The AD9484 also provides a data clock output (DCO) intended

for capturing the data in an external register. The data outputs

are valid on the rising edge of DCO.

The lowest conversion rate of the AD9484 is 50 MSPS. At clock

rates below 1 MSPS, the AD9484 assumes the standby mode.

VREF

The AD9484 VREF pin (Pin 31) allows the user to monitor the

on-board voltage reference, or provide an external reference

(requires configuration through the SPI). The three optional

settings are internal VREF (pin is connected to 20 kΩ to ground),

export VREF, and import VREF. Do not attach a bypass capacitor

to this pin. VREF is internally compensated and additional

loading may impact performance.

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