Data Sheet

AD9434

Rev. B | Page 11 of 28

PIN 1

INDICATOR

1

D3/D9–

2

D3/D9+

3

D4/D10–

4

D4/D10+

5

D5/D11–

6

D5/D11+

7

DRVDD

8

DRGND

9

OR–

10

OR+

11

DNC

12

DNC

13

DNC

14

DNC

35 VIN+

36 VIN–

37 AVDD

38 AVDD

39 AVDD

40 CML

41 AVDD

42 AVDD

34 AVDD

33 AVDD

32 AVDD

31 VREF

30 AVDD

29 PWDN

TOP VIEW

(Not to Scale)

PIN 0 (EXPOSED PADDLE) = AGND

AD9434

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. AGND AND DRGND SHOULD BE TIED TO A COMMON

QUIET GROUND PLANE.

3. THE EXPOSED PADDLE MUST BE SOLDERED TO

A GROUND PLANE.

Figure 5. Pin Configuration—Double Data Rate Mode

Table 8. Pin Function Descriptions—Double Data Rate Mode

Pin No.

Mnemonic

Description

0

AGND1

Analog Ground. The exposed paddle must be soldered to a ground plane.

30, 32 to 34, 37 to 39, 41

to 43, 46

AVDD

1.8 V Analog Supply.

7, 24, 47

DRVDD

1.8 V Digital Output Supply.

8, 23, 48

DRGND1

Digital Output Ground.

35

VIN+

Analog Input—True.

36

VIN−

Analog Input—Complement.

40

CML

Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized

internal bias voltage for VIN+/VIN−.

44

CLK+

Clock Input—True.

45

CLK−

Clock Input—Complement.

31

VREF

Voltage Reference Internal/Input/Output. Nominally 0.75 V.

25

SDIO

Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).

26

SCLK/DFS

Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).

27

CSB

Serial Port Chip Select (Active Low).

29

PWDN

Chip Power-Down.

49

DCO−

Data Clock Output—Complement.

50

DCO+

Data Clock Output—True.

51

D0/D6−

D0/D6 Complement Output (LSB).

52

D0/D6+

D0/D6 True Output (LSB).

53

D1/D7−

D1/D7 Complement Output.

54

D1/D7+

D1/D7 True Output.

55

D2/D8−

D2/D8 Complement Output.

56

D2/D8+

D2/D8 True Output.

1

D3/D9−

D3/D9 Complement Output.

2

D3/D9+

D3/D9 True Output.

3

D4/D10−

D4/D10 Complement Output.

4

D4/D10+

D4/D10 True Output.

5

D5/D11−

D5/D11 Complement Output (MSB).