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AD9655

Data Sheet

An on-chip, common-mode dc voltage reference is included in

the design and is available from the VCM pin. The VCM pin

must be bypassed to ground by a 0.1 µF capacitor, as described

in the Applications Information section. VCM error vs. load

current is shown in Figure 48.

–18

–16

–14

–12

–10

–8

–6

–4

–2

0.5

1.0

1.5

2.0

2.5

LOAD CURRENT (mA)

Figure 48. VCM Error vs. Load Current

Differential Input Configurations

There are several ways to drive the AD9655 either actively or

passively. However, optimum performance is achieved by

driving the analog inputs differentially. Using a differential

double balun configuration to drive the AD9655 provides

excellent performance and a flexible interface to the ADC for

baseband applications (see Figure 53).

For applications where SNR is a key parameter, differential

transformer coupling is the recommended input configuration (see

Figure 54) because the noise performance of most amplifiers is not

adequate to achieve the true performance of the AD9655.

Regardless of the configuration, the value of the shunt capacitor,

C, is dependent on the input frequency and may need to be

reduced or removed.

It is not recommended to drive the AD9655 inputs single-ended.

VOLTAGE REFERENCE

A stable and accurate 1.0 V to 1.4 V dc voltage reference is built

into the AD9655. Externally bypass the VREF pin to ground

with a low ESR, 1.0 μF capacitor in parallel with a low ESR,

0.1 μF ceramic capacitor.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9655, the largest input span available is 2.8 V p-p, which is

achieved by setting VREF to 1.4 V.

If the internal reference of the AD9655 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 49 and

Figure 50 show how the internal reference voltage is affected by

loading. It is recommended that VREF not be used to drive the

reference voltage of other devices at 1.4 V. Figure 51 and

Figure 52 show the typical drift characteristics of the internal

reference.

The internal buffer generates the positive and negative full-scale

references for the ADC core. A digital reset using Register 0x08

must follow any programmatic change in internal analog VREF.

–60

–40

–50

–30

–20

–10

2.0

2.5

0.5

1.0

1.5

LOAD CURRENT (mA)

INTERNAL VREF = 1V

Figure 49. VREF Error vs. Load Current, VREF = 1.0 V

–70

–60

–40

–50

–30

–20

–10

2.0

2.5

0.5

1.0

1.5

LOAD CURRENT (mA)

INTERNAL VREF = 1.4V

Figure 50. VREF Error vs. Load Current, VREF = 1.4 V

–0.006

–0.008

–0.002

–0.004

0.002

0.004

–40

–20

TEMPERATURE (°C)

INTERNAL VREF = 1V

Figure 51. Typical VREF Drift, VREF = 1.0 V

Rev. 0 | Page 20 of 37

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