AD9652

Data Sheet

Rev. B | Page 32 of 36

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 17 are not currently supported for this device.

Table 17. Memory Map Registers

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default

Notes/

Comments

Chip Configuration Registers

0x00

SPI port

config-

uration

(global)1

0

LSB first

Soft reset

1

1

Soft reset

LSB first

0

0x18

The nibbles

are mirrored

so that LSB

first mode

or MSB first

mode

registers

correctly,

regardless

of shift

mode

0x01

Chip ID

(global)

8-Bit Chip ID[7:0], (AD9652 = 0xC1) (default)

0xC1

Read only

0x02

Chip grade

(global)

Speed grade ID,

0x00: default

0x00

Speed

grade ID

differ-

entiates

devices;

read only

Channel Index and Transfer Registers

0x05

Channel

index

(global)

Channel B

(default)

Channel A

(default)

0x03

Bits are

set to

determine

which

device on

the chip

receives

the next

write

command;

applies to

local

registers

only

0xFF

Transfer

(global)

Transfer

0x00

Synchro-

nously

transfers

data from

the master

shift register

to the slave

ADC Functions

0x08

Power

modes

(local)

Reserved,

set to 1

External

power-

down pin

function

(local)

0 =

power-

down

1=

standby

Internal power-down

mode (local)

00 = normal operation

01 = full power-down

10 = standby

11 = reserved

0x80

Controls

power-

down

options

0x09

Global clock

(global)

Enable

DCS

(default)

0x01