AD9625 datasheet(66/74 Pages) AD

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AD9625

Data Sheet

Rev. C | Page 64 of 72

Table 81. JESD204B Configuration Register, Address 0x07A (Default = 0xC5)

Bit No.

Access

Bit Description

[7:0]

JESD204B serial checksum value for Lane 2. This value is automatically calculated. The value = (the sum of all link

configuration parameters for Lane 2) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.

Table 82. JESD204B Configuration Register, Address 0x07B (Default = 0xC6)

Bit No.

Access

Bit Description

[7:0]

JESD204B serial checksum value for Lane 3. This value is automatically calculated. The value = (the sum of all link

configuration parameters for Lane 3) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.

Table 83. JESD204B Configuration Register, Address 0x07C (Default = 0xC7)

Bit No.

Access

Bit Description

[7:0]

JESD204B serial checksum value for Lane 4. This value is automatically calculated. The value = (the sum of all link

configuration parameters for Lane 4) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.

Table 84. JESD204B Configuration Register, Address 0x07D (Default = 0xC8)

Bit No.

Access

Bit Description

[7:0]

JESD204B serial checksum value for Lane 5. This value is automatically calculated. The value = (the sum of all link

configuration parameters for Lane 5) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.

Table 85. JESD204B Configuration Register, Address 0x07E (Default = 0xC9)

Bit No.

Access

Bit Description

[7:0]

JESD204B serial checksum value for Lane 6. This value is automatically calculated. The value = (the sum of all link

configuration parameters for Lane 6) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.

Table 86. JESD204B Configuration Register, Address 0x07F (Default = 0xCA)

Bit No.

Access

Bit Description

[7:0]

JESD204B serial checksum value for Lane 6. This value is automatically calculated. The value = (the sum of all link

configuration parameters for Lane 6) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.

Table 87. JESD204B Lane Power-Down Register, Address 0x080 (Default = 0x00)

Bit No.

Access

Bit Description

Physical Lane H power-down.

0: Lane H enabled.

1: Lane H powered down.

Physical Lane G power-down.

0: Lane G enabled.

1: Lane G powered down.

Physical Lane F power-down.

0: Lane F enabled.

1: Lane F powered down.

Physical Lane E power-down.

0: Lane E enabled.

1: Lane E powered down.

Physical Lane D power-down.

0: Lane D enabled.

1: Lane D powered down.

Physical Lane C power-down.

0: Lane C enabled.

1: Lane C powered down.

Physical Lane B power-down.

0: Lane B enabled.

1: Lane B powered down.

Physical Lane A power-down.

0: Lane A enabled.

1: Lane A powered down.

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