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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD7656ABSTZ датащи(PDF) 6 Page - Analog Devices |
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AD7656ABSTZ датащи(HTML) 6 Page - Analog Devices |
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6 / 29 page  Data Sheet AD7656A TIMING SPECIFICATIONS AVCC and DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. For the ±4 × VREF range, VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V, and for the ±2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to −16.5 V. Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Table 2. Parameter Limit at TMIN, TMAX Unit Description1 VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25V PARALLEL INTERFACE MODE tCONVERT 3 3 µs typ Conversion time, internal clock tQUIET 150 150 ns min Minimum quiet time required between bus relinquish and start of next conversion tACQ 550 550 ns min Acquisition time t1 60 60 ns min CONVST x high to BUSY high t10 25 25 ns min Minimum CONVST x low pulse tWAKE-UP 2 2 ms max STBY rising edge to CONVST x rising edge, not shown in figures 25 25 µs max Partial power-down mode PARALLEL WRITE OPERATION t11 15 15 ns min WR pulse width t12 0 0 ns min CS to WR setup time t13 5 5 ns min CS to WR hold time t14 5 5 ns min Data setup time before WR rising edge t15 5 5 ns min Data hold after WR rising edge PARALLEL READ OPERATION t2 0 0 ns min BUSY to RD delay t3 0 0 ns min CS to RD setup time t4 0 0 ns min CS to RD hold time t5 45 36 ns min RD pulse width t6 45 36 ns max Data access time after RD falling edge t7 10 10 ns min Data hold time after RD rising edge t8 12 12 ns max Bus relinquish time after RD rising edge t9 6 6 ns min Minimum time between reads SERIAL INTERFACE MODE fSCLK 18 18 MHz max Frequency of serial read clock t16 12 12 ns max Delay from CS until SDATA three-state disabled t172 22 22 ns max Data access time after SCLK rising edge/CS falling edge t18 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t19 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t20 10 10 ns min SCLK to data valid hold time after SCLK falling edge t21 18 18 ns max CS rising edge to SDATA high impedance 1 Multifunction pin names may be referenced by their relevant function only. 2 A buffer is used on the data output pins for this measurement. 200µA IOL 200µA IOH 1.6V TO OUTPUT PIN CL 25pF Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 5 of 28 |
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