AD4020 datasheet(21/37 Pages) AD

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AD4020

Data Sheet

Rev. A | Page 20 of 36

RC Filter Values

The value of the RC filter (represented by R and C in Figure 31

to Figure 33 and Figure 36) and driving amplifier can be

selected depending on the input signal bandwidth of interest

at the full 1.8 MSPS throughput. Lower input signal bandwidth

means that the RC cutoff can be lower, thereby reducing noise

into the converter. For optimum performance at various

throughputs, use the recommended RC values (200 Ω, 180 pF)

and the ADA4807-1.

The RC values in Table 10 are chosen for ease of drive considera-

tions and greater ADC input protection. The combination of a

large R value (200 Ω) and small C value results in a reduced

dynamic load for the amplifier to drive. The smaller value of C

means less stability and phase margin concerns with the

amplifier. The large value of R limits the current into the ADC

input when the amplifier output exceeds the ADC input range.

DRIVER AMPLIFIER CHOICE

Although the AD4020 is easy to drive, the driver amplifier must

meet the following requirements:

•

The noise generated by the driver amplifier must be kept

low enough to preserve the SNR and transition noise

performance of the AD4020. The noise from the driver is

filtered by the single-pole, low-pass filter of the analog input

circuit of the AD4020 made by RIN and CIN, or by the

external filter, if one is used. Because the typical noise of

the AD4020 is 31.5 µV rms, the SNR degradation due to

the amplifier is

















−

)

(

31.5

log

LOSS

SNR

where:

f−3 dB is the input bandwidth, in megahertz, of the AD4020

(10 MHz) or the cutoff frequency of the input filter, if one

is used.

N is the noise gain of the amplifier (for example, 1 in buffer

configuration).

eN is the equivalent input noise voltage of the op amp in

nV/√Hz.

•

For ac applications, the driver must have a THD performance

commensurate with the AD4020.

•

For multichannel multiplexed applications, the driver

amplifier and the analog input circuit of the AD4020 must

settle for a full-scale step onto the capacitor array at a 20-bit

level (0.00001%, 1 ppm). In the data sheet of the amplifier,

settling at 0.1% to 0.01% is more commonly specified. This

may differ significantly from the settling time at a 20-bit

level and must be verified prior to driver selection.

Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths

Input Signal

Bandwidth (kHz)

R (Ω)

C (pF)

Recommended

Amplifier

Recommended Fully Differential

Amplifier

<10

See the High-Z Mode

section

See the High-Z Mode

section

See the High-Z Mode

section

ADA4940-1

<200

200

180

ADA4807-1

ADA4940-1

>200

200

120

ADA4897-1

ADA4932-1

Multiplexed

200

120

ADA4897-1

ADA4932-1

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