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LM9800 датащи(PDF) 21 Page - National Semiconductor (TI) |
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LM9800 датащи(HTML) 21 Page - National Semiconductor (TI) |
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21 / 34 page ![]() Configuration Register t MCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (t MCLK = 50ns). (Continued) TABLE 2. Configuration Register Parameters (Continued) Parameter Control Bits Result Dummy Pixels Note: Minimum Value is 1. Actual number of dummy pixels in CCD should be one less than number in this register. BLS7 BLS6 BLS5 BLS4 BLS3 BLS2 BLS1 BLS0 00000000 Not Valid 00000001 0 00000010 1 •••••••• • •••••••• • •••••••• • 11111110 253 11111111 254 Optical Black Pixels Note: Minimum Value is 1 BLL7 BLL6 BLL5 BLL4 BLL3 BLL2 BLL1 BLL0 00000000 Not Valid 00000001 1 00000010 2 •••••••• • •••••••• • •••••••• • 11111110 254 11111111 255 Internal PGA Gain Coefficient GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 0000000 0 [0 dB] 0000001 1 ••••••• • ••••••• • ••••••• • 1111110 126 1111111 127 [6 dB] PGA Gain PGASRC Coefficient 0 Internal Source 1 External Power Down PD 0 Operating 1 Power Down Offset Add OFF ADD 0 Offset z0 LSB 1 Offset z+1 LSB Master VGA Control VGA 0 VGA Disabled 1 VGA Enabled VGA State for Pixel “c” VGA c 0 VGA bypassed 1 VGA on VGA State for Pixel “b” VGA b 0 VGA bypassed 1 VGA on 21 www.national.com |
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