ECT25S40LP1CR datasheet(16/46 Pages) E-CMOS

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E-CMOS Corp. (www.ecmos.com.tw)

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4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

Configuration and Status Instructions

Write Enable (06H)

See Figure 5, the Write Enable instruction is for setting the Write Enable Latch bit. Th

e Write

Enable Latch bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip

Eraseand Write Status Register instruction. The Write Enable instruction sequence: /CS

goes low sending the Write Enable instruction /CS goes high.

Figure 5. Write Enable Sequence Diagram

Write Disable (04H)

See Figure 6, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write

Disable instruction sequence: /CS goes low

Sending the Write Disable instruction /CS goes

high.The WEL bit is reset by following condition:Power-up and upon completion of the Write

status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions.

Figure 6. Write Disable Sequence Diagram

Read Status Register (05H or 35H)

See Figure7 the Read Status Register (RDSR) instruction is for reading the Status Register.

The Status Register maybe read at any time, even while a Program, Erase or Write Status

check the Write in Progress (WIP) bit before sending a new instruction to the device. It is also

possible to read the Status Register continuously.

For instruction code “05H”, the SO will

output Status Register bits

S7~S0. The instruction code “35H”, the SO will output Status

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