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CY7C024/0241
CY7C025/0251
Document #: 38-06035 Rev. *B
Page 8 of 20
Data Retention Mode
The CY7C024/0241 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the min-
imum operating voltage (4.5 volts).
Notes:
16. Test conditions used are Load 2.
17. tBDD is a calculated parameter and is the greater of tWDD– tPWE (actual) or
tDDD– tSD (actual).
18. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not
tested.
BUSY TIMING[16]
tBLA
BUSY LOW from Address
Match
15
20
20
45
ns
tBHA
BUSY HIGH from Address
Mismatch
15
20
20
40
ns
tBLC
BUSY LOW from CE LOW
15
20
20
40
ns
tBHC
BUSY HIGH from CE HIGH
15
20
20
35
ns
tPS
Port Set-Up for Priority
5
5
5
5
ns
tWB
R/W HIGH after BUSY
(Slave)
0
0
0
0
ns
tWH
R/W HIGH after BUSY
HIGH (Slave)
13
20
30
40
ns
tBDD
[17]
BUSY HIGH to Data Valid
Note 17
Note 17
Note 17
Note 17
ns
INTERRUPT TIMING[16]
tINS
INT Set Time
15
20
25
30
ns
tINR
INT Reset Time
15
20
25
30
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE
or SEM)
10
12
15
20
ns
tSWRD
SEM Flag Write to Read
Time
5
10
10
15
ns
tSPS
SEM Flag Contention
Window
5
10
10
15
ns
tSAA
SEM Address Access Time
15
25
35
55
ns
Switching Characteristics Over the Operating Range[10] (continued)
7C024/0241–15
7C025/0251–15
7C024/0241–25
7C025/0251–25
7C024/0241–35
7C025/0251–35
7C024/0241–55
7C025/0251–55
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Timing
Parameter
Test Conditions[18]
Max.
Unit
ICCDR1
@ VCCDR = 2V
1.5
mA
Data Retention Mode
7C024–13
4.5V
4.5V
VCC > 2.0V
VCC to VCC – 0.2V
VCC
CE
tRC
V
IH
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