ADV7174BCP datasheet(39/52 Pages) AD

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ADV7174/ADV7179

Rev. A | Page 39 of 52

APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS

The ADV7174/ADV7179 is a highly integrated circuit contain-

ing both precision analog and high speed digital circuitry. It has

been designed to minimize interference effects on the integrity

of the analog circuitry by the high speed digital circuitry. It is

imperative that these same design and layout techniques be

applied to the system-level design so that high speed, accurate

performance is achieved. Figure 54 shows the analog interface

between the device and monitor.

The layout should be optimized for lowest noise on the

ADV7174/ADV7179 power and ground lines by shielding the

digital inputs and providing good decoupling. The lead length

between groups of VAA and GND pins should be minimized to

reduce inductive ringing.

GROUND PLANES

The ground plane should encompass all ADV7174/ADV7179

ground pins, voltage reference circuitry, power supply bypass

circuitry for the ADV7174/ADV7179, the analog output traces,

and all the digital signal traces leading up to the ADV7174/

ADV7179. The ground plane is the board’s common ground

plane.

POWER PLANES

The ADV7174/ADV7179 and any associated analog circuitry

should have its own power plane, referred to as the analog

power plane (VAA). This power plane should be connected to

the regular PCB power plane (VCC) at a single point through a

ferrite bead. This bead should be located within 3 inches of the

ADV7174/ADV7179.

The metallization gap separating the device power plane and

board power plane should be as narrow as possible to minimize

the obstruction to the flow of heat from the device into the

general board.

The PCB power plane should provide power to all digital logic

on the PC board, and the analog power plane should provide

power to all ADV7174/ADV7179 power pins and voltage

reference circuitry.

Plane-to-plane noise coupling can be reduced by ensuring that

portions of the regular PCB power and ground planes do not

overlay portions of the analog power plane unless they can be

arranged so that the plane-to-plane noise is common mode.

(FERRITE BEAD)

Ω

3.3 V (VCC)

150

Ω

3.3 V (VCC)

MPU BUS

3–5, 35–39

0.1

µF

0.01

µF

0.1

µF

3.3 V (VAA)

0.1

µF

3.3V (VAA)

10k

Ω

3.3 V (VAA)

27MHz CLOCK

(SAME CLOCK AS USED BY

MPEG2 DECODER)

POWER SUPPLY DECOUPLING

FOR EACH POWER SUPPLY GROUP

µF

GND

3.3 V

(VCC)

GND

ALSB

HSYNC

FIELD/VSYNC

BLANK

RESET

CLOCK

RSET

SDATA

SCLOCK

DAC B

DAC C

VAA

VREF

COMP

P7–P0

3.3 V (VAA)

Ω

SCRESET/RTC

ADV7174/ADV7179

UNUSED

INPUTS

SHOULD BE

GROUNDED

DAC A

100

Ω

100

Ω

RESET

TTX

TTXREQ

100k

Ω

100k

Ω

3.3 V (VCC)

TTX

TTXREQ

TELETEXT PULL-UP AND

PULL-DOWN RESISTORS

SHOULD ONLY BE USED

IF THESE PINS ARE NOT

CONNECTED

Ω

3.3 V (VAA)

100nF

Figure 54. Recommended Analog Circuit Layout

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