AD7734

Rev. 0 | Page 24 of 32

Dump Mode

When the DUMP bit in the mode register is set to 1, the channel

status register will be read immediately by a read of the channel

data register, regardless of whether the status or the data register

has been addressed through the communications register. The

DIN pin should not be high while reading 24-bit data in dump

mode; otherwise, the AD7734 will be reset.

Figure 18 shows the digital interface signals executing a single

conversion on Channel 0, waiting for the RDY pin to go low,

and reading the Channel 0 status register and data register in

the dump mode.

Continuous Conversion Mode

When the mode register is being written, the ADC status byte is

cleared and the RDY pin goes high, regardless of its previous

state. When the continuous conversion command is written to

the mode register, the ADC starts conversion on the channel

selected by the address of the mode register.

After the conversion is complete, the relevant channel data

register and channel status register are updated, the relevant

RDY bit in the ADC status register is set, and the AD7734

continues converting on the next enabled channel. The part will

cycle through all enabled channels until put into another mode

or reset. The cycle period will be the sum of all enabled

channels’ conversion times, set by the corresponding channel

conversion time registers.

The RDY bit is reset when the relevant channel data register is

being read. The behavior of the RDY pin depends on the

RDYFN bit in the I/O port register. When the RDYFN bit is 0,

the RDY pin goes low when any channel has unread data. When

the RDYFN bit is set to 1, the RDY pin will only go low if all

enabled channels have unread data.

If an ADC conversion result has not been read before a new

ADC conversion is completed, the new result will overwrite the

previous one. The relevant RDY bit goes low and the RDY pin

goes high for at least 163 MCLK cycles (~26.5 µs), indicating

when the data register is updated, and the previous conversion

data is lost.

If the data register is being read as an ADC conversion

completes, the data register will not be updated with the new

result (to avoid data corruption) and the new conversion

data is lost.

Figure 19 shows the digital interface signal’s sequence for the

continuous conversion mode with Channels 0 and 1 enabled

and the RDYFN bit set to 0. The RDY pin goes low and the data

register is read after each conversion. Figure 20 shows a similar

sequence but with the RDYFN bit set to 1. The RDY pin goes

low and all data registers are read after all conversions are

completed. Figure 21 shows the RDY pin when no data are read

from the AD7734.

DIN

SCLK

CS

DOUT

WRITE

COMMUNICATIONS

REGISTER

WRITE

MODE

REGISTER

RDY

CONVERSION TIME

READ DATA

REGISTER

READ

CHANNEL

STATUS

38h

48h

48h

WRITE

COMMUNICATIONS

REGISTER

(00h)

(00h)

(00h)

STATUS

DATA

DATA

Figure 18. Serial Interface Signals—Single Conversion Command, 16-Bits Data Reading, Dump Mode

SERIAL

INTERFACE

START

CONTINUOUS

CONVERSION

RDY

CH0 CONVERSION

READ

DATA

CH1

CH1 CONVERSION

CH0 CONVERSION

READ

DATA

CH0

CH1 CONVERSION

READ

DATA

CH0

CH0 CONVERSION

READ

DATA

CH1

Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 0