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iC-MB4

BiSS INTERFACE MASTER

Rev B2, Page 11/40

OPERATING REQUIREMENTS: µC Interface, INTEL mode

Operating conditions: CFGSPI = 0, INT_NMOT = 1, VDD = 3.0 . . . 5.5 V, Tj = -40 . . . 125 °C

lo input level = 0 . . . 0.8 V, hi input level = 2.0 V . . . VDD, lo output level = 0 . . . 0.4 V, hi output level = 2.4 V . . . VDD

Alias: NRD = NRD_RNW, NWR = NWR_E

Item

Symbol

Parameter

Conditions

Unit

No.

Min.

Max.

I001 tsCA

Setup Time:

NCS lo before ALE hi→lo

10

ns

I002 tsDA

Setup Time:

Data stable before ALE hi→lo

15

ns

I003 thDA

Hold Time:

Data stable after ALE hi→lo

15

ns

I004 tAh

Signal Duration:

ALE at high level

10

ns

I005 tsAR

Setup Time:

ALE lo before NRD hi→lo

10

ns

I006 thAR

Hold Time:

ALE lo after NRD lo→hi

NCS = lo

10

ns

I007 tRl

Signal Duration:

NRD at low level

NCS = lo

10

ns

I008 tpRD1

Propagation Delay:

Data stable after NRD hi→lo

NCS = lo, CL = 50 pF

25

ns

I009 tpRD2

Propagation Delay:

Data bus high impedance after NRD

lo→hi

NCS = lo, CL = 50 pF

25

ns

I010 thCR

Hold Time:

NCS lo after NRD lo→hi

10

ns

I011 tsAW

Setup Time:

ALE lo before NWR hi→lo

10

ns

I012 thAW

Hold Time:

ALE lo after NWR lo→hi

NCS = lo

10

ns

I013 tWl

Signal Duration:

NWR at low level

NCS = lo

10

ns

I014 tsDW

Setup Time:

Data stable before NWR lo→hi

NCS = lo

15

ns

I015 thDW

Hold Time:

Data stable after NWR lo→hi

NCS = lo

15

ns

I016 thCW

Hold Time:

NCS lo after NWR lo→hi

10

ns

Figure 3: Read cycle (Intel mode)

Figure 4: Write cycle (Intel mode)