RT5508 datasheet(21/57 Pages) RICHTEK

21 / 57 page

RT5508

is a registered trademark of Richtek Technology Corporation

DS5508-01

March

2017

www.richtek.com

The following sub-clauses explain the function of each

sub-block.

Look-Ahead Delay Buffer

Look-ahead delay can be programed from 0 up to 480

samples, which is up to 10ms at 48k sampling rate.

This delay should contain stereo gain synchronization

delay.

Gain Processing on the Data Path

The level control, limiting for protection, and the volume

control are implemented by multiplying the signal on

the data path, with the gain generated from the control

path.

Pilot

The pilot signal, with constant magnitude (30mV) is

added at the last stage of data path. The frequency of

pilot is fixed fp = 50Hz.

The pilot is disabled at PWDN/SUSPD/Off/Fault/Mute

mode.

A register control bit can be configured to set if the pilot

is also turned off in Silence mode. If yes, then the pilot

should be turn off after signal power below threshold for

SilenceResetTime. This bit also defines if the DC

resistance is monitored or not in Silence mode.

Except for Fault mode, the pilot always turned on or

turned off at zero cross level. In worst case the pilot

turn-off latency will be 11.6ms.

Signal Detector

The signal activity is detected when the input signal

level is above a user defined threshold. The detection

window can be specified to be 5ms/10ms/20ms.

Another long time constant: SilenceRestTime is used to

ensure the silence happen and set the ALC to its initial

gain.

Parameters :

sThresAct : silence or active threshold (0 to

90dBFS,

-6dB step)

SilenceResetTime : the time to reset ALC gain to initial

value (0 to 15 seconds)

Peak Detector

The peak detector monitors the peak of the signal

magnitude and the estimated excursion. The algorithm

is describe as following equation, with attack time can

be specified as 0ms/1ms/2ms/4ms and release time

can be specified by (1-RT) represented in 16-

bit 2’s

complement format.

xPeak(n) = (1-AT) xPeak(n-1)+AT

x(n)

xPeak(n) = (1-RT) xPeak(n-1)





for

x(n) >xPeak(n-1)

x(n)

xPeak(n-1)



Automatic Level Control (ALC)

The core of ALC gain control is depicted in Figure 15.

The gain is checked and adjusted every ALC_period,

which is specified by UpDoubleTime and DnHalfTime

registers. These two register bit fields has physical

meaning which mapped to approximately ±6dB per

second. They can be specified from 1/16 to 15.9375

seconds with resolution of 1/16s.

The internal logic implements ALC_period by a counter

expired every 16*UpDoubleTime or 16*DnHalfTime

when the gain is going up/dn respectively. Depend on

the clock base of I2S, the nominal of ±6dB per second

for double/half the gain is actually approximately by:

44.1k : 20*log10((4097/4096)^(48000/16)) = 6.36dB;

20*log10((4095/4096)^(48000/16)) = -6.36dB

48k : 20*log10((4097/4096)^(44100/16)) = 5.84dB;

20*log10((4095/4096)^(44100/16)) = -5.84dB

The Parameters for ALC Control :

sThresALC[7:0] : Threshold of signal, specified by 0 to1.

1 corresponds to the maximum allowable signal

specified by clipper module.

xThresALC[7:0] : Threshold of excursion, specified by

0~1.

1 corresponds to the maximum

allowable

excursion.

sThresALC and xThresALC are 8-bit unsigned number

representing the value 1/128~1, 0x80 is normalized to

UpDoubleTime[7:0]

gain

double

time

UpDoubleTime /16 (seconds)

DnHalfTime[7:0] : gain half time = DnHalfTime /16

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