Integrated

Circuit

Systems, Inc.

874004AG

www.icst.com/products/hiperclocks.html

REV. A JANUARY 21, 2005

7

ICS874004

PRELIMINARY

3.3V

R1

50

R3

50

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

R2

50

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

R3

125

R2

84

Zo = 50 Ohm

3.3V

R4

125

LVPECL

R1

84

3.3V

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both V

V

face examples for the HiPerClockS CLK/nCLK input driven by

the most common driver types. The input interfaces suggested

here are examples only. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

For example in

Figure 3A, the input termination applies for ICS

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

1.8V

R2

50

Input

LVHSTL Driver

ICS

HiPerClockS

R1

50

LVHSTL

3.3V

Zo = 50 Ohm

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

Zo = 50 Ohm

R1

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

A general LVDS interface is shown in

Figure 4. In a 100

Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100

Ω across near

100 Ohm Differiential Transmission Line

R1

100

3.3V

+

-

LVDS_Driv er

3.3V

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

un-used outputs.