X5643/X5645

Characteristics subject to change without notice.

2 of 19

REV 1.1.1 3/5/01

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PIN CONFIGURATION

Pin

PDIP

Pin

SOIC

Pin

TSSOP

Name

Function

1

2 & 3

2

CS/WDI

Chip Select Input. CS HIGH, deselects the device and the SO output pin is

at a high impedance state. Unless a nonvolatile write cycle is underway, the

device will be in the standby power mode. CS LOW enables the device, plac-

ing it in the active power mode. Prior to the start of any operation after power

up, a HIGH to LOW transition on CS is required.

Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watch-

dog timer. The absence of a HIGH to LOW transition within the watchdog time

out period results in RESET/RESET going active.

24

3

SO

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data

out on this pin. The falling edge of the serial clock (SCK) clocks the data out.

5

9

13

SI

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and

memory data on this pin. The rising edge of the serial clock (SCK) latches the in-

put data. Send all opcodes (Table 1), addresses and data MSB first.

6

10

14

SCK

Serial Clock. The serial clock controls the serial bus timing for data input and

output. The rising edge of SCK latches in the opcode, address, or data bits

present on the SI pin. The falling edge of SCK changes the data output on the

SO pin.

35

7

WP

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to

“lock” the setting of the watchdog timer control and the memory write protect bits.

46

8

Ground

8

12 & 13

19

Supply Voltage

7

11

18

RESET/

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output

200ms. RESET/RESET goes active if the watchdog timer is enabled and CS

remains either HIGH or LOW longer than the selectable watchdog time out

period. A falling edge of CS will reset the watchdog timer. RESET/RESET

goes active on power up at about 1V and remains active for 200ms after the

power supply stabilizes.

1, 7, 8,

14

1, 4–6,

9–12,

15–17, 20

NC

No internal connections

8-Lead PDIP

CS/WDI

WP

SO

1

2

3

4

RESET/RESET

8

7

6

5

14-Lead SOIC

SO

WP

1

2

3

4

5

6

7

RESET/RESET

SCK

SI

14

13

12

11

10

9

8

NC

NC

X5643/45

SCK

SI

CS/WDI

NC

X5643/45

NC

CS/WDI