WM8978GEFLSLASHV datasheet(62/78 Pages) WOLFSON

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WM8978

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PP Rev 1.7 January 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

GPIO1SEL

000

CSB/GPIO1 pin function select:

000= input (CSB/jack detection:

depending on MODE setting)

001= reserved

010=Temp ok

011=Amute active

100=PLL clk o/p

101=PLL lock

110=logic 1

111=logic 0

GPIO1POL

GPIO1 Polarity invert

0=Non inverted

1=Inverted

GPIO

Control

5:4

OPCLKDIV

PLL Output clock division ratio

00=divide by 1

01=divide by 2

10=divide by 3

11=divide by 4

Table 52 CSB/GPIO Control

Note: If MODE is set to 3 wire mode, CSB/GPIO1 shall be used as CSB input irrespective of the

GPIO1SEL[2:] bits.

For further details of the Jack detect operation see the OUTPUT SWITCHING section.

OUTPUT SWITCHING (JACK DETECT)

When the device is configured with a 2-wire interface the CSB/GPIO1 pin can be used as a switch

control input to automatically disable one set of outputs and enable another. The L2/GPIO2 and

R2/GPIO3 pins can also be used for this purpose. For example, when a headphone is plugged into

a jack socket then it may be desirable to disable the speaker (e.g. when one of the GPIO pins is

connected to a mechanical switch in the headphone socket to detect plug-in).

The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output

enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a

slow clock with period 2

21 x MCLK.

Note that the GPIOPOL bits are not relevant for jack detection, it is the signal detected at the pin

which is used.

The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2,

OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and

OUT4_EN_0 are the output enable signal which are used if the selected jack detection pin is at logic

0 (after de-bounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output

enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce).

Similar to the output enables, VMID can be driven out of OUT3. This VMID output can be configured

to be on/off depending on the jack detection input polarity of the VMID_EN_0 and VMID_EN_1 bits.

The jack detection enables work as follows:

All OUT_EN signals have an AND function performed with their normal enable signals (in Table 40).

When an output is normally enabled at per Table 40, the selected jack detection enable (controlled

by selected jack detection pin polarity) is set 0, it will turn the output off. If the normal enable signal is

already OFF (0), the jack detection signal will have no effect due on the AND function.

During jack detection if the user desires an output to be un-changed whether the jack is in or not,

both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000.

The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the

VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should

set to 0 for all JD_EN0 or JD_EN1 settings.

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