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WM8972LEFL/R датащи(PDF) 9 Page - Wolfson Microelectronics plc

номер детали WM8972LEFL/R
подробное описание детали  MONO CODEC FOR PORTABLE AUDIO APPLICATIONS
PDF  49 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8972LEFL/R датащи(HTML) 9 Page - Wolfson Microelectronics plc

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Preliminary Technical Data
WM8972L
w
PTD Rev 2.2 June 2004
9
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25
oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
TMCLKL
21
ns
MCLK System clock pulse width low
TMCLKH
21
ns
MCLK System clock cycle time
TMCLKY
54
ns
MCLK duty cycle
TMCLKDS
60:40
40:60
Test Conditions
CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25
oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
TMCLKL
10
ns
MCLK System clock pulse width low
TMCLKH
10
ns
MCLK System clock cycle time
TMCLKY
27
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
ADCDAT
ADCLRC/
DACLRC
(Outputs)
t
DL
DACDAT
t
DDA
t
DHT
t
DST
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)



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