WM8150

Production Data

w

PD Rev 3.0 November 2002

6

INPUT VIDEO SAMPLING

MCLK

VSMP

INPUT

VIDEO

t

PER

t

VSMPSU

t

VSMPH

t

VSU

t

VH

t

RSU

t

RH

t

MCLKL

t

MCLKH

Figure 1 Input Video Timing

Note:

1.

See Page 15 (Programmable VSMP Detect Circuit) for video sampling description.

Test Conditions

°C, MCLK = 16MHz unless otherwise stated.

PARAMETER

SYMBOLTEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK period

62.5

ns

MCLK high period

28.1

ns

MCLK low period

28.1

ns

VSMP set-up time

8ns

VSMP hold time

4ns

Video level set-up time

15

ns

Video level hold time

5ns

Reset level set-up time

15

ns

Reset level hold time

5ns

Notes:

1.

2.

Parameters are measured at 50% of the rising/falling edge.

OUTPUT DATA TIMING

MCLK

OP[3:0]

t

PD

t

PD

Figure 2 Output Data Timing

Test Conditions

°C, MCLK = 16MHz unless otherwise stated.

PARAMETER

SYMBOLTEST CONDITIONS

MIN

TYP

MAX

UNITS

Output propagation delay

30

ns