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D, DDA

TOP VIEW

THS3092

NC = No Internal Connection

D, PWP

TOP VIEW

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NC = No Internal Connection

THS3096

See Note A.

NC

REF

NC

NC

PD

NC

Note A: The devices with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF pin

DISSIPATION RATING TABLE

THS3092

THS3096

SLOS428A – DECEMBER 2003 – REVISED FEBRUARY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PART NUMBER

PACKAGE TYPE

TRANSPORT MEDIA, QUANTITY

THS3092D

Rails, 75

SOIC-8

THS3092DR

Tape and Reel, 2500

THS3092DDA

Rails, 75

THS3092DDAR

Tape and Reel, 2500

Power-down

THS3096D

Rails, 75

SOIC-8

THS3096DR

Tape and Reel, 2500

THS3096PWP

Rails, 90

THS3096PWPR

Tape and Reel, 2000

(1)

The PowerPAD is electrically isolated from all other pins.

PACKAGE

Θ

Θ

(1)

D-8

38.3

97.5

1.02 W

410 mW

9.2

45.8

2.18 W

873 mW

2.07

37.5

2.67 W

1.07 W

(1)

This data was taken using the JEDEC standard High-K test PCB.

(2)

Power rating is determined with a junction temperature of 125

°C. This is the point where distortion starts to substantially increase.

Thermal management of the final PCB should strive to keep the junction temperature at or below 125

°C for best performance and long

term reliability.

(3)

The THS3092 and THS3096 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be

connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction

temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the

PowerPAD™ thermally enhanced package.

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