THS3096 datasheet(21/34 Pages) TI

21 / 34 page

www.ti.com

PRINTED-CIRCUIT BOARD LAYOUT

500

1000

1500

2000

2500

100 k

1 M

10 M

100 M

1 G

−

1.21 k

Ω 1.21 kΩ

Ω VO

f − Frequency − Hz

VS = ±15 V and ±5 V

POWER-DOWN REFERENCE PIN

THS3092

THS3096

SLOS428A – DECEMBER 2003 – REVISED FEBRUARY 2004

TECHNIQUES FOR OPTIMAL

PERFORMANCE

Achieving optimum performance with high frequency

amplifier,

the

THS3092/6,

requires

careful

attention to board layout parasitic and external

component types.

Recommendations that optimize performance include:

•

Minimize parasitic capacitance to any ac ground

for all of the signal I/O pins. Parasitic capacitance

on the output and input pins can cause instability.

To reduce unwanted capacitance, a window

around the signal I/O pins should be opened in all

of the ground and power planes around those

Figure 65. Power-down Output Impedance vs

pins. Otherwise, ground and power planes should

Frequency

be unbroken elsewhere on the board.

•

Minimize the distance (< 0.25”) from the power

As with most current feedback amplifiers, the internal

supply pins to high frequency 0.1-µF and 100-pF

architecture places some limitations on the system

decoupling capacitors. At the device pins, the

when in power-down mode. Most notably is the fact

ground and power plane layout should not be in

that the amplifier actually turns ON if there is a

±0.7 V

close proximity to the signal I/O pins. Avoid

or greater difference between the two input nodes

narrow power and ground traces to minimize

(V+ and V-) of the amplifier. If this difference exceeds

inductance between the pins and the decoupling

±0.7 V, the output of the amplifier creates an output

capacitors. The power supply connections should

voltage

equal

approximately

always be decoupled with these capacitors.

[(V+ - V-) -0.7 V]

×Gain. This also implies that if a

Larger (6.8 µF or more) tantalum decoupling

voltage is applied to the output while in power-down

capacitors, effective at lower frequency, should

mode,

the

V-

node

voltage

equal

also be used on the main supply pins. These may

VO(applied)× RG/(RF + RG). For low gain configurations

be placed somewhat farther from the device and

and a large applied voltage at the output, the ampli-

may be shared among several devices in the

fier may actually turn ON due to the aforementioned

same area of the PC board.

behavior.

•

Careful selection and placement of external

The time delays associated with turning the device on

components preserve the high frequency per-

and off are specified as the time it takes for the

formance of the THS3092/6. Resistors should be

amplifier to reach either 10% or 90% of the final

a very low reactance type. Surface-mount re-

output voltage. The time delays are in the order of

sistors work best and allow a tighter overall

microseconds because the amplifier moves in and out

layout. Again, keep their leads and PC board

of the linear mode of operation in these transitions.

trace length as short as possible. Never use

wirebound type resistors in a high frequency

application. Since the output pin and inverting

OPERATION

input pins are the most sensitive to parasitic

capacitance, always position the feedback and

In addition to the power-down pin, the THS3096 and

series output resistors, if any, as close as poss-

THS3096 feature a reference pin (REF) which allows

ible to the inverting input pins and output pins.

the user to control the enable or disable power-down

Other network components, such as input termin-

voltage levels applied to the PD pin. In most

ation resistors, should be placed close to the

split-supply applications, the reference pin is connec-

gain-setting resistors. Even with a low parasitic

ted to ground. In either case, the user needs to be

capacitance

shunting

the

external

resistors,

aware of voltage-level thresholds that apply to the

excessively high resistor values can create sig-

power-down pin. The usable range at the REF pin is

nificant time constants that can degrade perform-

from VS- to (VS+ - 4 V).

ance. Good axial metal-film or surface-mount

resistors have approximately 0.2 pF in shunt with

the resistor. For resistor values > 2.0 k

Ω, this

parasitic capacitance can add a pole and/or a

zero that can effect circuit operation. Keep

resistor values as low as possible, consistent with

load driving considerations.

THS3096 датащи(PDF) 21 Page - Texas Instruments

THS3096 датащи(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

датащи скачать

ссылки URL