TA 235

4/6

AI03411

tCLAX

tCHAX

tWHDX

tDVWH

VALID SRD

A0-A10

G

DQ0-DQ7

RC

tCHWH

tWHRL

C1

W

RP

tPHWL

R1

tAVCL

tAVCH

R2

C2

tWLWH

tWHWL

RB

VPP

tVPHWH

tWHGL

tQVVPL

DIN1

DIN2

Write erase or

program setup

Write erase confirm or

valid address and data

Automated erase

or program delay

Read Status

Register Data

Ready to write

another command

tWLCH

The A/A Mux Interface bus operation is similar to

a standard flash programming protocol with the

exception that addressing is latched using the

Row/Column Select inputs. The lower address

signals (A0–A10) determine the Row Address bits

and

the

higher

address

signals

(A11-A18)

determine the Column Address bits. Figure 5

shows the Address/Address Multiplexed Interface

Read Protocol, and Figure 6 the Address/Address

Multiplexed Interface Write Protocol.

Firmware Security

Intel plans to add new security and software

functions to their chip-sets in a move that will boost

the profile of its future processors for the

multimedia and electronic markets. These are the

key features of the FWH that is basically a flash

with locks on its read and write capabilities that

can be opened using a cryptographic protocol.

The

hardware

security

functions

include

a

cryptographic

engine

to

authenticate

‘digital

certificates’ which Intel or a third party could load

in. The FWH could hold multiple certificates, each

able to grant specific features and ensure a

software program licensed to one user could not

be copied and run on another machine. In

addition, the certificates will act as unique serial

numbers, identifying a given machine in any

Internet or corporate network transaction.

Appendix 1

The Firmware Hub comes in two standard

packages of 32 pins PLCC (as shown in Figure 7)

and 40 pins TSOP (as shown in Figure 8).

References

1. Intel’s security plans raise fear from PC build-

ers, Rick Boyd-Merritt & Mark Carroll, EDTN

News, 15 Dec 1998.

Figure 6. Address/Address Multiplexed Interface Write Protocol