Integrated

Circuit

Systems, Inc.

ICS94222

This document is confidential and should not be released

without written consents from ICS.

94222 Rev - 5/10/01

Advance Information

ADVANCE INFORMATION documents contain information on products in the

formative or design phase development. Characteristic data and other

specifications are design goals. ICS reserves the right to change or discontinue

these products without notice.

Pin Configuration

Recommended Application:

BX, Appollo Pro 133 type of chip set.

Output Features:

•

3 - CPUs @2.5V, up to 166MHz.

•

17 - SDRAM @ 3.3V, up to 166MHz.

•

7 - PCI @3.3V

•

2 - IOAPIC @ 2.5V

•

1 - 48MHz, @3.3V fixed.

•

1 - 24MHz @ 3.3V

•

2 - REF @3.3V, 14.318MHz.

Features:

•

Programmable ouput frequency.

•

Programmable ouput rise/fall time.

•

Programmable PCI_F and PCICLK skew.

•

Spread spectrum for EMI control typically by 7dB to 8dB,

with programmable spread percentage.

•

Watchdog timer technology to reset system

if over-clocking causes malfunction.

•

Uses external 14.318MHz crystal.

•

FS pins for frequency select

Key Specifications:

•

CPU – CPU: <175ps

•

SDRAM - SDRAM: <500ps

•

PCI – PCI: <500ps

•

CPU-SDRAM: <500ps

•

CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns

Programmable System Frequency Generator for PII/III™

Block Diagram

Functionality

56-Pin SSOP

* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

AVDD

*FS2/REF1

*PCI_STOP#/REF0

GND

X1

X2

VDD

*MODE/PCICLK_F

*FS3/PCICLK0

GND

VDD

BUFFERIN

SDRAM11

SDRAM10

VDD

SDRAM9

SDRAM8

GND

SDRAM15

SDRAM14

GND

SDATA

SCLK

PCICLK1

PCICLK2

PCICLK3

PCICLK4

PCICLK5

VDDL

IOAPIC0

IOAPIC_F

GND

CPUCLK_F

CPUCLK0

VDDL

CPUCLK1

GND

CLK_STOP*

SDRAM_F

VDDSDR

SDRAM0

SDRAM1

GND

SDRAM2

SDRAM3

SDRAM4

SDRAM5

VDD

SDRAM6

SDRAM7

GND

SDRAM12

SDRAM13

AVDD48

24MHz/FS0*

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

3

S

F2

S

F1

S

F0

S

F

U

P

C

)

z

H

M

(

K

L

C

I

C

P

)

z

H

M

(

0000

0

0

.

0

80

0

.

0

4

000

1

0

0

.

5

70

5

.

7

3

00

1

0

1

3

.

3

85

6

.

1

4

00

11

9

.

6

65

4

.

3

3

01

0

0

0

0

.

3

0

13

3

.

4

3

01

01

1

0

.

2

1

14

3

.

7

3

01

1

0

1

0

.

8

61

0

.

4

3

0

111

7

.

0

0

17

5

.

3

3

1

000

0

0

.

0

2

10

0

.

0

4

10

0

1

9

9

.

4

1

13

3

.

8

3

10

10

9

9

.

9

0

16

6

.

6

3

10

1

1

0

0

.

5

0

10

0

.

5

3

11

00

0

0

.

0

4

10

0

.

5

3

11

0

1

0

0

.

0

5

10

5

.

7

3

111

0

0

0

.

4

2

10

0

.

1

3

1111

9

.

3

3

15

2

.

3

3

CLK_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz

IOAPIC0

CPUCLK (1:0)

CPUCLK_F

IOAPIC_F

SDRAM (15:0)

SDRAM_F

PCICLK (5:0)

PCICLK_F

X1

X2

XTAL

OSC

PCI

CLOCK

DIVDER

STOP

STOP

÷2

STOP

STOP

POR

SDATA

SCLK

FS (3:0)

MODE

Control

Logic

Config.

Reg.

REF [1:0]

24MHz

LATCH

1

2

16

66

BUFFERIN